2025-02-28 11:54:20 +01:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2025 AIROHA Inc
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* Author: Lorenzo Bianconi <lorenzo@kernel.org>
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*/
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#define NPU_NUM_CORES 8
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struct airoha_npu {
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struct device *dev;
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struct regmap *regmap;
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struct airoha_npu_core {
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struct airoha_npu *npu;
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/* protect concurrent npu memory accesses */
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spinlock_t lock;
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struct work_struct wdt_work;
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} cores[NPU_NUM_CORES];
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2025-05-16 10:00:00 +02:00
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struct airoha_foe_stats __iomem *stats;
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2025-02-28 11:54:20 +01:00
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struct {
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int (*ppe_init)(struct airoha_npu *npu);
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int (*ppe_deinit)(struct airoha_npu *npu);
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int (*ppe_flush_sram_entries)(struct airoha_npu *npu,
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dma_addr_t foe_addr,
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int sram_num_entries);
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int (*ppe_foe_commit_entry)(struct airoha_npu *npu,
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dma_addr_t foe_addr,
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u32 entry_size, u32 hash,
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bool ppe2);
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} ops;
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};
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2025-05-16 10:00:00 +02:00
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struct airoha_npu *airoha_npu_get(struct device *dev, dma_addr_t *stats_addr);
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2025-02-28 11:54:20 +01:00
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void airoha_npu_put(struct airoha_npu *npu);
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