2025-02-07 13:24:44 +05:30
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef __IRIS_STATE_H__
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#define __IRIS_STATE_H__
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2025-02-07 13:24:56 +05:30
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struct iris_inst;
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2025-02-07 13:24:44 +05:30
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/**
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* enum iris_core_state
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*
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* @IRIS_CORE_DEINIT: default state.
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* @IRIS_CORE_INIT: core state with core initialized. FW loaded and
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* HW brought out of reset, shared queues established
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* between host driver and firmware.
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* @IRIS_CORE_ERROR: error state.
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*
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* -----------
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* |
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* V
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* -----------
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* +--->| DEINIT |<---+
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* | ----------- |
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* | | |
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* | v |
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* | ----------- |
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* | / \ |
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* | / \ |
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* | / \ |
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* | v v v
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* ----------- -----------
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* | INIT |--->| ERROR |
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* ----------- -----------
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*/
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enum iris_core_state {
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IRIS_CORE_DEINIT,
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IRIS_CORE_INIT,
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IRIS_CORE_ERROR,
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};
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2025-02-07 13:24:56 +05:30
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/**
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* enum iris_inst_state
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*
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* @IRIS_INST_INIT: video instance is opened.
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* @IRIS_INST_INPUT_STREAMING: stream on is completed on output plane.
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* @IRIS_INST_OUTPUT_STREAMING: stream on is completed on capture plane.
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* @IRIS_INST_STREAMING: stream on is completed on both output and capture planes.
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* @IRIS_INST_DEINIT: video instance is closed.
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* @IRIS_INST_ERROR: error state.
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* |
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* V
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* -------------
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* +--------| INIT |----------+
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* | ------------- |
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* | ^ ^ |
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* | / \ |
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* | / \ |
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* | v v |
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* | ----------- ----------- |
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* | | INPUT OUTPUT | |
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* |---| STREAMING STREAMING |---|
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* | ----------- ----------- |
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* | ^ ^ |
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* | \ / |
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* | \ / |
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* | v v |
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* | ------------- |
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* |--------| STREAMING |-----------|
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* | ------------- |
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* | | |
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* | | |
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* | v |
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* | ----------- |
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* +-------->| DEINIT |<----------+
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* | ----------- |
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* | | |
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* | | |
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* | v |
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* | ---------- |
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* +-------->| ERROR |<------------+
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* ----------
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*/
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enum iris_inst_state {
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IRIS_INST_DEINIT,
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IRIS_INST_INIT,
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IRIS_INST_INPUT_STREAMING,
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IRIS_INST_OUTPUT_STREAMING,
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IRIS_INST_STREAMING,
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IRIS_INST_ERROR,
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};
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2025-02-07 13:25:01 +05:30
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#define IRIS_INST_SUB_STATES 8
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#define IRIS_INST_MAX_SUB_STATE_VALUE ((1 << IRIS_INST_SUB_STATES) - 1)
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/**
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* enum iris_inst_sub_state
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*
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* @IRIS_INST_SUB_FIRST_IPSC: indicates source change is received from firmware
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* when output port is not yet streaming.
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* @IRIS_INST_SUB_DRC: indicates source change is received from firmware
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* when output port is streaming and source change event is
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* sent to client.
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* @IRIS_INST_SUB_DRC_LAST: indicates last buffer is received from firmware
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* as part of source change.
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2025-02-07 13:25:03 +05:30
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* @IRIS_INST_SUB_DRAIN: indicates drain is in progress.
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* @IRIS_INST_SUB_DRAIN_LAST: indicates last buffer is received from firmware
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* as part of drain sequence.
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2025-02-07 13:25:01 +05:30
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* @IRIS_INST_SUB_INPUT_PAUSE: source change is received form firmware. This
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* indicates that firmware is paused to process
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* any further input frames.
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* @IRIS_INST_SUB_OUTPUT_PAUSE: last buffer is received form firmware as part
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* of drc sequence. This indicates that
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* firmware is paused to process any further output frames.
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2025-02-07 13:25:06 +05:30
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* @IRIS_INST_SUB_LOAD_RESOURCES: indicates all the resources have been loaded by the
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* firmware and it is ready for processing.
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2025-02-07 13:25:01 +05:30
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*/
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enum iris_inst_sub_state {
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IRIS_INST_SUB_FIRST_IPSC = BIT(0),
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IRIS_INST_SUB_DRC = BIT(1),
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IRIS_INST_SUB_DRC_LAST = BIT(2),
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IRIS_INST_SUB_DRAIN = BIT(3),
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IRIS_INST_SUB_DRAIN_LAST = BIT(4),
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IRIS_INST_SUB_INPUT_PAUSE = BIT(5),
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IRIS_INST_SUB_OUTPUT_PAUSE = BIT(6),
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IRIS_INST_SUB_LOAD_RESOURCES = BIT(7),
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};
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2025-02-07 13:24:56 +05:30
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int iris_inst_change_state(struct iris_inst *inst,
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enum iris_inst_state request_state);
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int iris_inst_change_sub_state(struct iris_inst *inst,
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enum iris_inst_sub_state clear_sub_state,
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enum iris_inst_sub_state set_sub_state);
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int iris_inst_state_change_streamon(struct iris_inst *inst, u32 plane);
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int iris_inst_state_change_streamoff(struct iris_inst *inst, u32 plane);
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int iris_inst_sub_state_change_drc(struct iris_inst *inst);
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int iris_inst_sub_state_change_drain_last(struct iris_inst *inst);
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int iris_inst_sub_state_change_drc_last(struct iris_inst *inst);
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int iris_inst_sub_state_change_pause(struct iris_inst *inst, u32 plane);
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bool iris_allow_cmd(struct iris_inst *inst, u32 cmd);
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2025-05-09 14:08:50 +05:30
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bool iris_drc_pending(struct iris_inst *inst);
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2025-02-07 13:24:56 +05:30
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2025-02-07 13:24:44 +05:30
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#endif
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