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132 lines
2.7 KiB
C
132 lines
2.7 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/clk.h>
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#include <linux/interconnect.h>
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#include <linux/pm_domain.h>
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#include <linux/pm_opp.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include "iris_core.h"
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#include "iris_resources.h"
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#define BW_THRESHOLD 50000
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int iris_set_icc_bw(struct iris_core *core, unsigned long icc_bw)
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{
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unsigned long bw_kbps = 0, bw_prev = 0;
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const struct icc_info *icc_tbl;
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int ret = 0, i;
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icc_tbl = core->iris_platform_data->icc_tbl;
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for (i = 0; i < core->icc_count; i++) {
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if (!strcmp(core->icc_tbl[i].name, "video-mem")) {
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bw_kbps = icc_bw;
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bw_prev = core->power.icc_bw;
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bw_kbps = clamp_t(typeof(bw_kbps), bw_kbps,
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icc_tbl[i].bw_min_kbps, icc_tbl[i].bw_max_kbps);
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if (abs(bw_kbps - bw_prev) < BW_THRESHOLD && bw_prev)
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return ret;
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core->icc_tbl[i].avg_bw = bw_kbps;
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core->power.icc_bw = bw_kbps;
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break;
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}
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}
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return icc_bulk_set_bw(core->icc_count, core->icc_tbl);
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}
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int iris_unset_icc_bw(struct iris_core *core)
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{
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u32 i;
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core->power.icc_bw = 0;
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for (i = 0; i < core->icc_count; i++) {
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core->icc_tbl[i].avg_bw = 0;
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core->icc_tbl[i].peak_bw = 0;
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}
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return icc_bulk_set_bw(core->icc_count, core->icc_tbl);
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}
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int iris_enable_power_domains(struct iris_core *core, struct device *pd_dev)
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{
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int ret;
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ret = dev_pm_opp_set_rate(core->dev, ULONG_MAX);
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if (ret)
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return ret;
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ret = pm_runtime_get_sync(pd_dev);
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if (ret < 0)
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return ret;
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return ret;
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}
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int iris_disable_power_domains(struct iris_core *core, struct device *pd_dev)
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{
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int ret;
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ret = dev_pm_opp_set_rate(core->dev, 0);
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if (ret)
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return ret;
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pm_runtime_put_sync(pd_dev);
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return 0;
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}
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static struct clk *iris_get_clk_by_type(struct iris_core *core, enum platform_clk_type clk_type)
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{
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const struct platform_clk_data *clk_tbl;
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u32 clk_cnt, i, j;
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clk_tbl = core->iris_platform_data->clk_tbl;
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clk_cnt = core->iris_platform_data->clk_tbl_size;
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for (i = 0; i < clk_cnt; i++) {
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if (clk_tbl[i].clk_type == clk_type) {
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for (j = 0; core->clock_tbl && j < core->clk_count; j++) {
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if (!strcmp(core->clock_tbl[j].id, clk_tbl[i].clk_name))
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return core->clock_tbl[j].clk;
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}
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}
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}
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return NULL;
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}
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int iris_prepare_enable_clock(struct iris_core *core, enum platform_clk_type clk_type)
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{
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struct clk *clock;
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clock = iris_get_clk_by_type(core, clk_type);
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if (!clock)
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return -EINVAL;
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return clk_prepare_enable(clock);
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}
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int iris_disable_unprepare_clock(struct iris_core *core, enum platform_clk_type clk_type)
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{
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struct clk *clock;
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clock = iris_get_clk_by_type(core, clk_type);
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if (!clock)
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return -EINVAL;
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clk_disable_unprepare(clock);
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return 0;
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}
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