2025-02-07 13:24:49 +05:30
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef __IRIS_BUFFER_H__
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#define __IRIS_BUFFER_H__
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#include <media/videobuf2-v4l2.h>
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struct iris_inst;
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#define to_iris_buffer(ptr) container_of(ptr, struct iris_buffer, vb2)
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/**
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* enum iris_buffer_type
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*
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* @BUF_INPUT: input buffer to the iris hardware
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* @BUF_OUTPUT: output buffer from the iris hardware
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* @BUF_BIN: buffer to store intermediate bin data
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* @BUF_ARP: buffer for auto register programming
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* @BUF_COMV: buffer to store colocated motion vectors
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* @BUF_NON_COMV: buffer to hold config data for HW
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* @BUF_LINE: buffer to store decoding/encoding context data for HW
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* @BUF_DPB: buffer to store display picture buffers for reference
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* @BUF_PERSIST: buffer to store session context data
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* @BUF_SCRATCH_1: buffer to store decoding/encoding context data for HW
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* @BUF_TYPE_MAX: max buffer types
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*/
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enum iris_buffer_type {
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BUF_INPUT = 1,
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BUF_OUTPUT,
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BUF_BIN,
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BUF_ARP,
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BUF_COMV,
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BUF_NON_COMV,
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BUF_LINE,
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BUF_DPB,
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BUF_PERSIST,
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BUF_SCRATCH_1,
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BUF_TYPE_MAX,
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};
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/*
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* enum iris_buffer_attributes
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*
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* BUF_ATTR_DEFERRED: buffer queued by client but not submitted to firmware.
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* BUF_ATTR_PENDING_RELEASE: buffers requested to be released from firmware.
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* BUF_ATTR_QUEUED: buffers submitted to firmware.
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* BUF_ATTR_DEQUEUED: buffers received from firmware.
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* BUF_ATTR_BUFFER_DONE: buffers sent back to vb2.
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*/
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enum iris_buffer_attributes {
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BUF_ATTR_DEFERRED = BIT(0),
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BUF_ATTR_PENDING_RELEASE = BIT(1),
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BUF_ATTR_QUEUED = BIT(2),
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BUF_ATTR_DEQUEUED = BIT(3),
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BUF_ATTR_BUFFER_DONE = BIT(4),
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};
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/**
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* struct iris_buffer
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*
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* @vb2: v4l2 vb2 buffer
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* @list: list head for the iris_buffers structure
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* @inst: iris instance structure
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* @type: enum for type of iris buffer
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* @index: identifier for the iris buffer
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* @fd: file descriptor of the buffer
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* @buffer_size: accessible buffer size in bytes starting from addr_offset
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* @data_offset: accessible buffer offset from base address
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* @data_size: data size in bytes
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* @device_addr: device address of the buffer
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* @kvaddr: kernel virtual address of the buffer
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* @dma_attrs: dma attributes
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* @flags: buffer flags. It is represented as bit masks.
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* @timestamp: timestamp of the buffer in nano seconds (ns)
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* @attr: enum for iris buffer attributes
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*/
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struct iris_buffer {
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struct vb2_v4l2_buffer vb2;
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struct list_head list;
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struct iris_inst *inst;
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enum iris_buffer_type type;
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u32 index;
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int fd;
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size_t buffer_size;
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u32 data_offset;
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size_t data_size;
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dma_addr_t device_addr;
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void *kvaddr;
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unsigned long dma_attrs;
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u32 flags; /* V4L2_BUF_FLAG_* */
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u64 timestamp;
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enum iris_buffer_attributes attr;
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};
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struct iris_buffers {
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struct list_head list;
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u32 min_count;
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u32 size;
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};
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int iris_get_buffer_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
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2025-02-07 13:24:59 +05:30
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void iris_get_internal_buffers(struct iris_inst *inst, u32 plane);
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int iris_create_internal_buffers(struct iris_inst *inst, u32 plane);
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int iris_queue_internal_buffers(struct iris_inst *inst, u32 plane);
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int iris_destroy_internal_buffer(struct iris_inst *inst, struct iris_buffer *buffer);
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2025-05-09 14:08:47 +05:30
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int iris_destroy_all_internal_buffers(struct iris_inst *inst, u32 plane);
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int iris_destroy_dequeued_internal_buffers(struct iris_inst *inst, u32 plane);
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2025-02-07 13:24:59 +05:30
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int iris_alloc_and_queue_persist_bufs(struct iris_inst *inst);
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2025-02-07 13:25:02 +05:30
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int iris_alloc_and_queue_input_int_bufs(struct iris_inst *inst);
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2025-02-07 13:24:59 +05:30
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int iris_queue_buffer(struct iris_inst *inst, struct iris_buffer *buf);
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2025-02-07 13:25:00 +05:30
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int iris_queue_deferred_buffers(struct iris_inst *inst, enum iris_buffer_type buf_type);
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int iris_vb2_buffer_done(struct iris_inst *inst, struct iris_buffer *buf);
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2025-02-07 13:24:49 +05:30
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void iris_vb2_queue_error(struct iris_inst *inst);
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#endif
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