2019-05-28 10:10:04 -07:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2013-03-22 16:34:02 +02:00
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/*
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* Tegra host1x Interrupt Management
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*
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2023-01-19 15:09:20 +02:00
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* Copyright (c) 2010-2021, NVIDIA Corporation.
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2013-03-22 16:34:02 +02:00
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*/
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#ifndef __HOST1X_INTR_H
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#define __HOST1X_INTR_H
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struct host1x;
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2023-01-19 15:09:20 +02:00
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struct host1x_syncpt_fence;
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2013-03-22 16:34:02 +02:00
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2024-05-31 10:07:18 +03:00
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struct host1x_intr_irq_data {
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struct host1x *host;
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u32 offset;
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};
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2013-03-22 16:34:02 +02:00
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/* Initialize host1x sync point interrupt */
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2023-01-19 15:09:20 +02:00
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int host1x_intr_init(struct host1x *host);
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2013-03-22 16:34:02 +02:00
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/* Deinitialize host1x sync point interrupt */
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void host1x_intr_deinit(struct host1x *host);
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/* Enable host1x sync point interrupt */
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void host1x_intr_start(struct host1x *host);
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/* Disable host1x sync point interrupt */
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void host1x_intr_stop(struct host1x *host);
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2023-01-19 15:09:20 +02:00
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void host1x_intr_handle_interrupt(struct host1x *host, unsigned int id);
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void host1x_intr_add_fence_locked(struct host1x *host, struct host1x_syncpt_fence *fence);
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bool host1x_intr_remove_fence(struct host1x *host, struct host1x_syncpt_fence *fence);
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2013-03-22 16:34:02 +02:00
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#endif
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