2024-11-25 10:21:18 +10:00
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/* SPDX-License-Identifier: MIT
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*
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* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef __NVKM_FSP_PRIV_H__
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#define __NVKM_FSP_PRIV_H__
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#define nvkm_fsp(p) container_of((p), struct nvkm_fsp, subdev)
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#include <subdev/fsp.h>
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struct nvkm_fsp_func {
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int (*wait_secure_boot)(struct nvkm_fsp *);
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struct {
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u32 version;
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u32 size_hash;
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u32 size_pkey;
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u32 size_sig;
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int (*boot_gsp_fmc)(struct nvkm_fsp *, u64 args_addr, u32 rsvd_size, bool resume,
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u64 img_addr, const u8 *hash, const u8 *pkey, const u8 *sig);
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} cot;
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};
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int nvkm_fsp_new_(const struct nvkm_fsp_func *,
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struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fsp **);
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2024-11-25 10:27:02 +10:00
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int gh100_fsp_wait_secure_boot(struct nvkm_fsp *);
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2024-11-25 10:21:18 +10:00
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int gh100_fsp_boot_gsp_fmc(struct nvkm_fsp *, u64 args_addr, u32 rsvd_size, bool resume,
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u64 img_addr, const u8 *hash, const u8 *pkey, const u8 *sig);
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#endif
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