linux/drivers/gpu/drm/nouveau/include/nvif/if0021.h

/* SPDX-License-Identifier: MIT */
#ifndef __NVIF_IF0021_H__
#define __NVIF_IF0021_H__

union nvif_cgrp_args {
	struct nvif_cgrp_v0 {
		__u8  version;
		__u8  namelen;
		__u8  runlist;
		__u8  pad03[3];
		__u16 cgid;
		__u64 vmm;
		__u8  name[];
	} v0;
};
#endif
drm/nouveau/fifo: add new channel classes Exposes a bunch of the new features that became possible as a result of the earlier commits. DRM will build on this in the future to add support for features such as SCG ("async compute") and multi-device rendering, as part of the work necessary to be able to write a half- decent vulkan driver - finally. For the moment, this just crudely ports DRM to the API changes. - channel class interfaces now the same for all HW classes - channel group class exposed (SCG) - channel runqueue selector exposed (SCG) - channel sub-device id control exposed (multi-device rendering) - channel names in logging will reflect creating process, not fd owner - explicit USERD allocation required by VOLTA_CHANNEL_GPFIFO_A and newer - drm is smarter about determining the appropriate channel class to use Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com> 2022-06-01 20:47:38 +10:00			`/* SPDX-License-Identifier: MIT */`
			`#ifndef __NVIF_IF0021_H__`
			`#define __NVIF_IF0021_H__`

			`union nvif_cgrp_args {`
			`struct nvif_cgrp_v0 {`
			`__u8 version;`
			`__u8 namelen;`
			`__u8 runlist;`
			`__u8 pad03[3];`
			`__u16 cgid;`
			`__u64 vmm;`
			`__u8 name[];`
			`} v0;`
			`};`
			`#endif`