2019-06-03 07:44:50 +02:00
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// SPDX-License-Identifier: GPL-2.0-only
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drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 12:44:06 -04:00
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/*
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2014-12-08 10:48:57 -05:00
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* Copyright (c) 2014 The Linux Foundation. All rights reserved.
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drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 12:44:06 -04:00
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*/
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2022-06-14 12:54:49 +03:00
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#include <drm/drm_fourcc.h>
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#include <drm/drm_framebuffer.h>
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drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 12:44:06 -04:00
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#include "msm_drv.h"
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2013-11-30 14:58:23 -05:00
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#include "mdp_kms.h"
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drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 12:44:06 -04:00
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2014-12-08 10:48:57 -05:00
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static struct csc_cfg csc_convert[CSC_MAX] = {
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[CSC_RGB2RGB] = {
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.type = CSC_RGB2RGB,
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.matrix = {
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0x0200, 0x0000, 0x0000,
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0x0000, 0x0200, 0x0000,
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0x0000, 0x0000, 0x0200
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},
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.pre_bias = { 0x0, 0x0, 0x0 },
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.post_bias = { 0x0, 0x0, 0x0 },
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.pre_clamp = { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff },
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.post_clamp = { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff },
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},
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[CSC_YUV2RGB] = {
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.type = CSC_YUV2RGB,
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.matrix = {
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0x0254, 0x0000, 0x0331,
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0x0254, 0xff37, 0xfe60,
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0x0254, 0x0409, 0x0000
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},
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.pre_bias = { 0xfff0, 0xff80, 0xff80 },
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.post_bias = { 0x00, 0x00, 0x00 },
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.pre_clamp = { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff },
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.post_clamp = { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff },
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},
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[CSC_RGB2YUV] = {
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.type = CSC_RGB2YUV,
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.matrix = {
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0x0083, 0x0102, 0x0032,
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0x1fb5, 0x1f6c, 0x00e1,
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0x00e1, 0x1f45, 0x1fdc
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},
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.pre_bias = { 0x00, 0x00, 0x00 },
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.post_bias = { 0x10, 0x80, 0x80 },
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.pre_clamp = { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff },
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.post_clamp = { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0 },
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},
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[CSC_YUV2YUV] = {
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.type = CSC_YUV2YUV,
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.matrix = {
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0x0200, 0x0000, 0x0000,
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0x0000, 0x0200, 0x0000,
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0x0000, 0x0000, 0x0200
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},
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.pre_bias = { 0x00, 0x00, 0x00 },
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.post_bias = { 0x00, 0x00, 0x00 },
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.pre_clamp = { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff },
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.post_clamp = { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff },
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},
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};
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2024-04-20 07:01:05 +03:00
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#define MDP_TILE_HEIGHT_DEFAULT 1
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#define MDP_TILE_HEIGHT_UBWC 4
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#define MDP_TILE_HEIGHT_NV12 8
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#define INTERLEAVED_RGB_FMT(fmt, a, r, g, b, e0, e1, e2, e3, uc, alpha, \
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bp, flg, fm, np) \
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{ \
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.pixel_format = DRM_FORMAT_ ## fmt, \
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.fetch_type = MDP_PLANE_INTERLEAVED, \
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.alpha_enable = alpha, \
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.element = { (e0), (e1), (e2), (e3) }, \
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.bpc_g_y = g, \
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.bpc_b_cb = b, \
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.bpc_r_cr = r, \
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.bpc_a = a, \
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.chroma_sample = CHROMA_FULL, \
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.unpack_count = uc, \
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.bpp = bp, \
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.fetch_mode = fm, \
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.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
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.num_planes = np, \
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.tile_height = MDP_TILE_HEIGHT_DEFAULT \
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}
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#define INTERLEAVED_RGB_FMT_TILED(fmt, a, r, g, b, e0, e1, e2, e3, uc, \
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alpha, bp, flg, fm, np, th) \
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{ \
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.pixel_format = DRM_FORMAT_ ## fmt, \
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.fetch_type = MDP_PLANE_INTERLEAVED, \
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.alpha_enable = alpha, \
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.element = { (e0), (e1), (e2), (e3) }, \
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.bpc_g_y = g, \
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.bpc_b_cb = b, \
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.bpc_r_cr = r, \
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.bpc_a = a, \
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.chroma_sample = CHROMA_FULL, \
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.unpack_count = uc, \
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.bpp = bp, \
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.fetch_mode = fm, \
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.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
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.num_planes = np, \
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.tile_height = th \
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}
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#define INTERLEAVED_YUV_FMT(fmt, a, r, g, b, e0, e1, e2, e3, \
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alpha, chroma, count, bp, flg, fm, np) \
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{ \
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.pixel_format = DRM_FORMAT_ ## fmt, \
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.fetch_type = MDP_PLANE_INTERLEAVED, \
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.alpha_enable = alpha, \
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.element = { (e0), (e1), (e2), (e3)}, \
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.bpc_g_y = g, \
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.bpc_b_cb = b, \
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.bpc_r_cr = r, \
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.bpc_a = a, \
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.chroma_sample = chroma, \
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.unpack_count = count, \
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.bpp = bp, \
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.fetch_mode = fm, \
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.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
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.num_planes = np, \
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.tile_height = MDP_TILE_HEIGHT_DEFAULT \
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}
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#define PSEUDO_YUV_FMT(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np) \
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{ \
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.pixel_format = DRM_FORMAT_ ## fmt, \
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.fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
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.alpha_enable = 0, \
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.element = { (e0), (e1), 0, 0 }, \
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.bpc_g_y = g, \
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.bpc_b_cb = b, \
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.bpc_r_cr = r, \
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.bpc_a = a, \
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.chroma_sample = chroma, \
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.unpack_count = 2, \
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.bpp = 2, \
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.fetch_mode = fm, \
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.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
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.num_planes = np, \
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.tile_height = MDP_TILE_HEIGHT_DEFAULT \
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}
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#define PSEUDO_YUV_FMT_TILED(fmt, a, r, g, b, e0, e1, chroma, \
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flg, fm, np, th) \
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{ \
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.pixel_format = DRM_FORMAT_ ## fmt, \
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.fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
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.alpha_enable = 0, \
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.element = { (e0), (e1), 0, 0 }, \
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.bpc_g_y = g, \
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.bpc_b_cb = b, \
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.bpc_r_cr = r, \
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.bpc_a = a, \
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.chroma_sample = chroma, \
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.unpack_count = 2, \
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.bpp = 2, \
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.fetch_mode = fm, \
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.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
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.num_planes = np, \
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.tile_height = th \
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}
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#define PSEUDO_YUV_FMT_LOOSE(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np)\
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{ \
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.pixel_format = DRM_FORMAT_ ## fmt, \
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.fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
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.alpha_enable = 0, \
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.element = { (e0), (e1), 0, 0 }, \
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.bpc_g_y = g, \
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.bpc_b_cb = b, \
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.bpc_r_cr = r, \
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.bpc_a = a, \
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.chroma_sample = chroma, \
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.unpack_count = 2, \
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.bpp = 2, \
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.fetch_mode = fm, \
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.flags = MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB | flg, \
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.num_planes = np, \
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.tile_height = MDP_TILE_HEIGHT_DEFAULT \
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2014-12-08 10:48:57 -05:00
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}
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drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 12:44:06 -04:00
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2024-04-20 07:01:05 +03:00
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#define PSEUDO_YUV_FMT_LOOSE_TILED(fmt, a, r, g, b, e0, e1, chroma, \
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flg, fm, np, th) \
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{ \
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.pixel_format = DRM_FORMAT_ ## fmt, \
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.fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
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.alpha_enable = 0, \
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.element = { (e0), (e1), 0, 0 }, \
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.bpc_g_y = g, \
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.bpc_b_cb = b, \
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.bpc_r_cr = r, \
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.bpc_a = a, \
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.chroma_sample = chroma, \
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.unpack_count = 2, \
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.bpp = 2, \
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.fetch_mode = fm, \
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.flags = MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB | flg, \
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.num_planes = np, \
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.tile_height = th \
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}
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#define PLANAR_YUV_FMT(fmt, a, r, g, b, e0, e1, e2, alpha, chroma, bp, \
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flg, fm, np) \
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{ \
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.pixel_format = DRM_FORMAT_ ## fmt, \
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.fetch_type = MDP_PLANE_PLANAR, \
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.alpha_enable = alpha, \
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.element = { (e0), (e1), (e2), 0 }, \
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.bpc_g_y = g, \
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.bpc_b_cb = b, \
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.bpc_r_cr = r, \
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.bpc_a = a, \
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.chroma_sample = chroma, \
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.unpack_count = 1, \
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.bpp = bp, \
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.fetch_mode = fm, \
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.flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
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.num_planes = np, \
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.tile_height = MDP_TILE_HEIGHT_DEFAULT \
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}
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static const struct msm_format mdp_formats[] = {
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INTERLEAVED_RGB_FMT(ARGB8888,
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BPC8A, BPC8, BPC8, BPC8,
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C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
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true, 4, 0,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(ABGR8888,
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BPC8A, BPC8, BPC8, BPC8,
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C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
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true, 4, 0,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(XBGR8888,
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BPC8A, BPC8, BPC8, BPC8,
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C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
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false, 4, 0,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(RGBA8888,
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BPC8A, BPC8, BPC8, BPC8,
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C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
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true, 4, 0,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(BGRA8888,
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BPC8A, BPC8, BPC8, BPC8,
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C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
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true, 4, 0,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(BGRX8888,
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BPC8A, BPC8, BPC8, BPC8,
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C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
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false, 4, 0,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(XRGB8888,
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BPC8A, BPC8, BPC8, BPC8,
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C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
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false, 4, 0,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(RGBX8888,
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BPC8A, BPC8, BPC8, BPC8,
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C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
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false, 4, 0,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(RGB888,
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0, BPC8, BPC8, BPC8,
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C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
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false, 3, 0,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(BGR888,
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0, BPC8, BPC8, BPC8,
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C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
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false, 3, 0,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(RGB565,
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0, BPC5, BPC6, BPC5,
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C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
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false, 2, 0,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(BGR565,
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0, BPC5, BPC6, BPC5,
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C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
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false, 2, 0,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(ARGB1555,
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BPC1A, BPC5, BPC5, BPC5,
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C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
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true, 2, 0,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(ABGR1555,
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BPC1A, BPC5, BPC5, BPC5,
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C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
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true, 2, 0,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(RGBA5551,
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BPC1A, BPC5, BPC5, BPC5,
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C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
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true, 2, 0,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(BGRA5551,
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BPC1A, BPC5, BPC5, BPC5,
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C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
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true, 2, 0,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(XRGB1555,
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BPC1A, BPC5, BPC5, BPC5,
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C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
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false, 2, 0,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(XBGR1555,
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BPC1A, BPC5, BPC5, BPC5,
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C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
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false, 2, 0,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(RGBX5551,
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BPC1A, BPC5, BPC5, BPC5,
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C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
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false, 2, 0,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(BGRX5551,
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BPC1A, BPC5, BPC5, BPC5,
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C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
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false, 2, 0,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(ARGB4444,
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BPC4A, BPC4, BPC4, BPC4,
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C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
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true, 2, 0,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(ABGR4444,
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BPC4A, BPC4, BPC4, BPC4,
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C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
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true, 2, 0,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(RGBA4444,
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BPC4A, BPC4, BPC4, BPC4,
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C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
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true, 2, 0,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(BGRA4444,
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BPC4A, BPC4, BPC4, BPC4,
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C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
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true, 2, 0,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(XRGB4444,
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BPC4A, BPC4, BPC4, BPC4,
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C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
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false, 2, 0,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(XBGR4444,
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BPC4A, BPC4, BPC4, BPC4,
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C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
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false, 2, 0,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(RGBX4444,
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BPC4A, BPC4, BPC4, BPC4,
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C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
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false, 2, 0,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(BGRX4444,
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BPC4A, BPC4, BPC4, BPC4,
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C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
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false, 2, 0,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(BGRA1010102,
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BPC8A, BPC8, BPC8, BPC8,
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C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
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true, 4, MSM_FORMAT_FLAG_DX,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(RGBA1010102,
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BPC8A, BPC8, BPC8, BPC8,
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C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
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true, 4, MSM_FORMAT_FLAG_DX,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(ABGR2101010,
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BPC8A, BPC8, BPC8, BPC8,
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C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
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true, 4, MSM_FORMAT_FLAG_DX,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(ARGB2101010,
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BPC8A, BPC8, BPC8, BPC8,
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C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
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true, 4, MSM_FORMAT_FLAG_DX,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(XRGB2101010,
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BPC8A, BPC8, BPC8, BPC8,
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C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
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false, 4, MSM_FORMAT_FLAG_DX,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(BGRX1010102,
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BPC8A, BPC8, BPC8, BPC8,
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C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
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false, 4, MSM_FORMAT_FLAG_DX,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(XBGR2101010,
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BPC8A, BPC8, BPC8, BPC8,
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C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
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false, 4, MSM_FORMAT_FLAG_DX,
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MDP_FETCH_LINEAR, 1),
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INTERLEAVED_RGB_FMT(RGBX1010102,
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BPC8A, BPC8, BPC8, BPC8,
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C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
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false, 4, MSM_FORMAT_FLAG_DX,
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MDP_FETCH_LINEAR, 1),
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2014-12-08 10:48:57 -05:00
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/* --- RGB formats above / YUV formats below this line --- */
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2015-07-06 16:35:31 -04:00
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/* 2 plane YUV */
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2024-04-20 07:01:05 +03:00
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PSEUDO_YUV_FMT(NV12,
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0, BPC8, BPC8, BPC8,
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C1_B_Cb, C2_R_Cr,
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CHROMA_420, MSM_FORMAT_FLAG_YUV,
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MDP_FETCH_LINEAR, 2),
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PSEUDO_YUV_FMT(NV21,
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0, BPC8, BPC8, BPC8,
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C2_R_Cr, C1_B_Cb,
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CHROMA_420, MSM_FORMAT_FLAG_YUV,
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MDP_FETCH_LINEAR, 2),
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PSEUDO_YUV_FMT(NV16,
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0, BPC8, BPC8, BPC8,
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C1_B_Cb, C2_R_Cr,
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CHROMA_H2V1, MSM_FORMAT_FLAG_YUV,
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MDP_FETCH_LINEAR, 2),
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PSEUDO_YUV_FMT(NV61,
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0, BPC8, BPC8, BPC8,
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C2_R_Cr, C1_B_Cb,
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CHROMA_H2V1, MSM_FORMAT_FLAG_YUV,
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MDP_FETCH_LINEAR, 2),
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PSEUDO_YUV_FMT_LOOSE(P010,
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0, BPC8, BPC8, BPC8,
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C1_B_Cb, C2_R_Cr,
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CHROMA_420, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_YUV,
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MDP_FETCH_LINEAR, 2),
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2015-07-06 16:35:31 -04:00
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/* 1 plane YUV */
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2024-04-20 07:01:05 +03:00
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INTERLEAVED_YUV_FMT(VYUY,
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0, BPC8, BPC8, BPC8,
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C2_R_Cr, C0_G_Y, C1_B_Cb, C0_G_Y,
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false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
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MDP_FETCH_LINEAR, 2),
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INTERLEAVED_YUV_FMT(UYVY,
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0, BPC8, BPC8, BPC8,
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C1_B_Cb, C0_G_Y, C2_R_Cr, C0_G_Y,
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false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
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MDP_FETCH_LINEAR, 2),
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INTERLEAVED_YUV_FMT(YUYV,
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0, BPC8, BPC8, BPC8,
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C0_G_Y, C1_B_Cb, C0_G_Y, C2_R_Cr,
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false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
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MDP_FETCH_LINEAR, 2),
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INTERLEAVED_YUV_FMT(YVYU,
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0, BPC8, BPC8, BPC8,
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|
|
C0_G_Y, C2_R_Cr, C0_G_Y, C1_B_Cb,
|
|
|
|
|
false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
|
|
|
|
|
MDP_FETCH_LINEAR, 2),
|
|
|
|
|
|
2015-07-06 16:35:31 -04:00
|
|
|
/* 3 plane YUV */
|
2024-04-20 07:01:05 +03:00
|
|
|
PLANAR_YUV_FMT(YUV420,
|
|
|
|
|
0, BPC8, BPC8, BPC8,
|
|
|
|
|
C2_R_Cr, C1_B_Cb, C0_G_Y,
|
|
|
|
|
false, CHROMA_420, 1, MSM_FORMAT_FLAG_YUV,
|
|
|
|
|
MDP_FETCH_LINEAR, 3),
|
|
|
|
|
|
|
|
|
|
PLANAR_YUV_FMT(YVU420,
|
|
|
|
|
0, BPC8, BPC8, BPC8,
|
|
|
|
|
C1_B_Cb, C2_R_Cr, C0_G_Y,
|
|
|
|
|
false, CHROMA_420, 1, MSM_FORMAT_FLAG_YUV,
|
|
|
|
|
MDP_FETCH_LINEAR, 3),
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* UBWC formats table:
|
|
|
|
|
* This table holds the UBWC formats supported.
|
|
|
|
|
* If a compression ratio needs to be used for this or any other format,
|
|
|
|
|
* the data will be passed by user-space.
|
|
|
|
|
*/
|
|
|
|
|
static const struct msm_format mdp_formats_ubwc[] = {
|
|
|
|
|
INTERLEAVED_RGB_FMT_TILED(BGR565,
|
|
|
|
|
0, BPC5, BPC6, BPC5,
|
|
|
|
|
C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
|
|
|
|
|
false, 2, MSM_FORMAT_FLAG_COMPRESSED,
|
|
|
|
|
MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
|
|
|
|
|
|
|
|
|
|
INTERLEAVED_RGB_FMT_TILED(ABGR8888,
|
|
|
|
|
BPC8A, BPC8, BPC8, BPC8,
|
|
|
|
|
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
|
|
|
|
|
true, 4, MSM_FORMAT_FLAG_COMPRESSED,
|
|
|
|
|
MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
|
|
|
|
|
|
|
|
|
|
/* ARGB8888 and ABGR8888 purposely have the same color
|
|
|
|
|
* ordering. The hardware only supports ABGR8888 UBWC
|
|
|
|
|
* natively.
|
|
|
|
|
*/
|
|
|
|
|
INTERLEAVED_RGB_FMT_TILED(ARGB8888,
|
|
|
|
|
BPC8A, BPC8, BPC8, BPC8,
|
|
|
|
|
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
|
|
|
|
|
true, 4, MSM_FORMAT_FLAG_COMPRESSED,
|
|
|
|
|
MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
|
|
|
|
|
|
|
|
|
|
INTERLEAVED_RGB_FMT_TILED(XBGR8888,
|
|
|
|
|
BPC8A, BPC8, BPC8, BPC8,
|
|
|
|
|
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
|
|
|
|
|
false, 4, MSM_FORMAT_FLAG_COMPRESSED,
|
|
|
|
|
MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
|
|
|
|
|
|
|
|
|
|
INTERLEAVED_RGB_FMT_TILED(XRGB8888,
|
|
|
|
|
BPC8A, BPC8, BPC8, BPC8,
|
|
|
|
|
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
|
|
|
|
|
false, 4, MSM_FORMAT_FLAG_COMPRESSED,
|
|
|
|
|
MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
|
|
|
|
|
|
|
|
|
|
INTERLEAVED_RGB_FMT_TILED(ABGR2101010,
|
|
|
|
|
BPC8A, BPC8, BPC8, BPC8,
|
|
|
|
|
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
|
|
|
|
|
true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
|
|
|
|
|
MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
|
|
|
|
|
|
|
|
|
|
INTERLEAVED_RGB_FMT_TILED(XBGR2101010,
|
|
|
|
|
BPC8A, BPC8, BPC8, BPC8,
|
|
|
|
|
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
|
|
|
|
|
true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
|
|
|
|
|
MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
|
|
|
|
|
|
|
|
|
|
INTERLEAVED_RGB_FMT_TILED(XRGB2101010,
|
|
|
|
|
BPC8A, BPC8, BPC8, BPC8,
|
|
|
|
|
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
|
|
|
|
|
true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
|
|
|
|
|
MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
|
|
|
|
|
|
|
|
|
|
/* XRGB2101010 and ARGB2101010 purposely have the same color
|
|
|
|
|
* ordering. The hardware only supports ARGB2101010 UBWC
|
|
|
|
|
* natively.
|
|
|
|
|
*/
|
|
|
|
|
INTERLEAVED_RGB_FMT_TILED(ARGB2101010,
|
|
|
|
|
BPC8A, BPC8, BPC8, BPC8,
|
|
|
|
|
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
|
|
|
|
|
true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
|
|
|
|
|
MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
|
|
|
|
|
|
|
|
|
|
PSEUDO_YUV_FMT_TILED(NV12,
|
|
|
|
|
0, BPC8, BPC8, BPC8,
|
|
|
|
|
C1_B_Cb, C2_R_Cr,
|
|
|
|
|
CHROMA_420, MSM_FORMAT_FLAG_YUV |
|
|
|
|
|
MSM_FORMAT_FLAG_COMPRESSED,
|
|
|
|
|
MDP_FETCH_UBWC, 4, MDP_TILE_HEIGHT_NV12),
|
|
|
|
|
|
|
|
|
|
PSEUDO_YUV_FMT_TILED(P010,
|
|
|
|
|
0, BPC8, BPC8, BPC8,
|
|
|
|
|
C1_B_Cb, C2_R_Cr,
|
|
|
|
|
CHROMA_420, MSM_FORMAT_FLAG_DX |
|
|
|
|
|
MSM_FORMAT_FLAG_YUV |
|
|
|
|
|
MSM_FORMAT_FLAG_COMPRESSED,
|
|
|
|
|
MDP_FETCH_UBWC, 4, MDP_TILE_HEIGHT_UBWC),
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 12:44:06 -04:00
|
|
|
};
|
|
|
|
|
|
2018-02-13 12:42:44 -05:00
|
|
|
const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format,
|
|
|
|
|
uint64_t modifier)
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 12:44:06 -04:00
|
|
|
{
|
2024-04-20 07:01:05 +03:00
|
|
|
const struct msm_format *map = NULL;
|
|
|
|
|
ssize_t map_size;
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 12:44:06 -04:00
|
|
|
int i;
|
2024-04-20 07:01:05 +03:00
|
|
|
|
|
|
|
|
switch (modifier) {
|
|
|
|
|
case 0:
|
|
|
|
|
map = mdp_formats;
|
|
|
|
|
map_size = ARRAY_SIZE(mdp_formats);
|
|
|
|
|
break;
|
|
|
|
|
case DRM_FORMAT_MOD_QCOM_COMPRESSED:
|
|
|
|
|
map = mdp_formats_ubwc;
|
|
|
|
|
map_size = ARRAY_SIZE(mdp_formats_ubwc);
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
drm_err(kms->dev, "unsupported format modifier %llX\n", modifier);
|
|
|
|
|
return NULL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < map_size; i++) {
|
|
|
|
|
const struct msm_format *f = &map[i];
|
|
|
|
|
|
2024-04-20 07:01:02 +03:00
|
|
|
if (f->pixel_format == format)
|
|
|
|
|
return f;
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 12:44:06 -04:00
|
|
|
}
|
2024-04-20 07:01:05 +03:00
|
|
|
|
|
|
|
|
drm_err(kms->dev, "unsupported fmt: %p4cc modifier 0x%llX\n",
|
|
|
|
|
&format, modifier);
|
|
|
|
|
|
drm/msm: basic KMS driver for snapdragon
The snapdragon chips have multiple different display controllers,
depending on which chip variant/version. (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.
To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.
The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently. But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge. This
would remove the 'msm_connector' base class. But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..
This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-06-26 12:44:06 -04:00
|
|
|
return NULL;
|
|
|
|
|
}
|
2014-12-08 10:48:57 -05:00
|
|
|
|
|
|
|
|
struct csc_cfg *mdp_get_default_csc_cfg(enum csc_type type)
|
|
|
|
|
{
|
2019-08-29 19:50:16 +03:00
|
|
|
if (WARN_ON(type >= CSC_MAX))
|
2014-12-08 10:48:57 -05:00
|
|
|
return NULL;
|
|
|
|
|
|
|
|
|
|
return &csc_convert[type];
|
|
|
|
|
}
|