2019-06-03 07:44:50 +02:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2018-06-27 15:26:09 -04:00
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/*
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* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*/
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#ifndef _DPU_PLANE_H_
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#define _DPU_PLANE_H_
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#include <drm/drm_crtc.h>
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#include "dpu_kms.h"
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#include "dpu_hw_mdss.h"
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#include "dpu_hw_sspp.h"
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/**
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* struct dpu_plane_state: Define dpu extension of drm plane state object
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* @base: base drm plane state object
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2023-03-16 19:16:28 +03:00
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* @pipe: software pipe description
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2023-03-16 19:16:48 +03:00
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* @r_pipe: software pipe description of the second pipe
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2023-03-16 19:16:41 +03:00
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* @pipe_cfg: software pipe configuration
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2023-03-16 19:16:48 +03:00
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* @r_pipe_cfg: software pipe configuration for the second pipe
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2018-06-27 15:26:09 -04:00
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* @stage: assigned by crtc blender
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2020-12-01 15:38:55 -08:00
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* @needs_qos_remap: qos remap settings need to be updated
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2018-06-27 15:26:09 -04:00
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* @multirect_index: index of the rectangle of SSPP
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* @multirect_mode: parallel or time multiplex multirect mode
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* @pending: whether the current update is still pending
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2020-07-16 17:05:34 +05:30
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* @plane_fetch_bw: calculated BW per plane
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* @plane_clk: calculated clk per plane
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2022-02-23 11:11:08 -08:00
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* @needs_dirtyfb: whether attached CRTC needs pixel data explicitly flushed
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2024-09-03 06:22:48 +03:00
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* @layout: framebuffer memory layout
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2018-06-27 15:26:09 -04:00
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*/
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struct dpu_plane_state {
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struct drm_plane_state base;
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2023-03-16 19:16:28 +03:00
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struct dpu_sw_pipe pipe;
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2023-03-16 19:16:48 +03:00
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struct dpu_sw_pipe r_pipe;
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2023-03-16 19:16:41 +03:00
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struct dpu_sw_pipe_cfg pipe_cfg;
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2023-03-16 19:16:48 +03:00
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struct dpu_sw_pipe_cfg r_pipe_cfg;
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2018-06-27 15:26:09 -04:00
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enum dpu_stage stage;
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2020-12-01 15:38:55 -08:00
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bool needs_qos_remap;
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2018-06-27 15:26:09 -04:00
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bool pending;
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2020-07-16 17:05:34 +05:30
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u64 plane_fetch_bw;
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u64 plane_clk;
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2022-02-23 11:11:08 -08:00
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bool needs_dirtyfb;
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2024-09-03 06:22:48 +03:00
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struct dpu_hw_fmt_layout layout;
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2018-06-27 15:26:09 -04:00
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};
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#define to_dpu_plane_state(x) \
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container_of(x, struct dpu_plane_state, base)
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void dpu_plane_flush(struct drm_plane *plane);
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void dpu_plane_set_error(struct drm_plane *plane, bool error);
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struct drm_plane *dpu_plane_init(struct drm_device *dev,
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2018-08-22 23:19:56 +05:30
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uint32_t pipe, enum drm_plane_type type,
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2022-02-09 20:24:56 +03:00
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unsigned long possible_crtcs);
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2018-06-27 15:26:09 -04:00
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2024-12-15 14:40:16 +02:00
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struct drm_plane *dpu_plane_init_virtual(struct drm_device *dev,
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enum drm_plane_type type,
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unsigned long possible_crtcs);
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int dpu_plane_color_fill(struct drm_plane *plane,
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uint32_t color, uint32_t alpha);
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2021-12-02 01:26:26 +03:00
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#ifdef CONFIG_DEBUG_FS
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void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable);
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#else
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static inline void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) {}
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#endif
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2024-12-15 14:40:16 +02:00
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int dpu_assign_plane_resources(struct dpu_global_state *global_state,
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struct drm_atomic_state *state,
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struct drm_crtc *crtc,
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struct drm_plane_state **states,
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unsigned int num_planes);
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2018-06-27 15:26:09 -04:00
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#endif /* _DPU_PLANE_H_ */
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