2020-02-25 13:15:07 +02:00
|
|
|
/* SPDX-License-Identifier: MIT */
|
|
|
|
/*
|
|
|
|
* Copyright © 2020 Intel Corporation
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef __INTEL_DRAM_H__
|
|
|
|
#define __INTEL_DRAM_H__
|
|
|
|
|
2025-05-27 12:25:26 +03:00
|
|
|
#include <linux/types.h>
|
|
|
|
|
2020-02-25 13:15:07 +02:00
|
|
|
struct drm_i915_private;
|
2025-05-27 12:25:22 +03:00
|
|
|
struct drm_device;
|
2025-05-27 12:25:26 +03:00
|
|
|
|
|
|
|
struct dram_info {
|
|
|
|
bool wm_lv_0_adjust_needed;
|
|
|
|
u8 num_channels;
|
|
|
|
bool symmetric_memory;
|
|
|
|
enum intel_dram_type {
|
|
|
|
INTEL_DRAM_UNKNOWN,
|
|
|
|
INTEL_DRAM_DDR3,
|
|
|
|
INTEL_DRAM_DDR4,
|
|
|
|
INTEL_DRAM_LPDDR3,
|
|
|
|
INTEL_DRAM_LPDDR4,
|
|
|
|
INTEL_DRAM_DDR5,
|
|
|
|
INTEL_DRAM_LPDDR5,
|
|
|
|
INTEL_DRAM_GDDR,
|
|
|
|
INTEL_DRAM_GDDR_ECC,
|
|
|
|
__INTEL_DRAM_TYPE_MAX,
|
|
|
|
} type;
|
|
|
|
u8 num_qgv_points;
|
|
|
|
u8 num_psf_gv_points;
|
|
|
|
};
|
2020-02-25 13:15:07 +02:00
|
|
|
|
|
|
|
void intel_dram_edram_detect(struct drm_i915_private *i915);
|
2025-05-27 12:25:25 +03:00
|
|
|
int intel_dram_detect(struct drm_i915_private *i915);
|
2024-06-14 12:22:37 +03:00
|
|
|
unsigned int i9xx_fsb_freq(struct drm_i915_private *i915);
|
2025-05-27 12:25:22 +03:00
|
|
|
const struct dram_info *intel_dram_info(struct drm_device *drm);
|
2020-02-25 13:15:07 +02:00
|
|
|
|
|
|
|
#endif /* __INTEL_DRAM_H__ */
|