2021-11-22 13:15:03 +02:00
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2021 Intel Corporation
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*/
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#ifndef __VLV_DSI_H__
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#define __VLV_DSI_H__
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enum port;
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2024-10-29 23:52:12 +02:00
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struct intel_crtc_state;
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2025-03-21 12:52:45 +02:00
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struct intel_display;
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2021-11-22 13:15:03 +02:00
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struct intel_dsi;
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2023-09-12 14:06:40 +03:00
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#ifdef I915
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2021-11-22 13:15:03 +02:00
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void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
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2024-10-29 23:52:12 +02:00
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int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state);
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2025-03-21 12:52:45 +02:00
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void vlv_dsi_init(struct intel_display *display);
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2023-09-12 14:06:40 +03:00
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#else
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static inline void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
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{
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}
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2024-10-29 23:52:12 +02:00
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static inline int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state)
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{
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return 0;
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}
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2025-03-21 12:52:45 +02:00
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static inline void vlv_dsi_init(struct intel_display *display)
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2023-09-12 14:06:40 +03:00
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{
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}
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#endif
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2021-11-22 13:15:03 +02:00
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#endif /* __VLV_DSI_H__ */
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