public-mirrors/linux
1
0
Fork 0
mirror of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2025-08-05 16:54:27 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions
linux/drivers/gpu/drm/i915/display/intel_vdsc_regs.h

355 lines
17 KiB
C
Raw Permalink Normal View History

drm/i915/display: split out DSC and DSS registers Relatively few places need the DSC and DSS register definitions. Move them to intel_vdsc_regs.h. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230301151949.1591501-1-jani.nikula@intel.com
2023-03-01 17:19:49 +02:00
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2023 Intel Corporation
*/
#ifndef __INTEL_VDSC_REGS_H__
#define __INTEL_VDSC_REGS_H__
#include "intel_display_reg_defs.h"
/* Display Stream Splitter Control */
#define DSS_CTL1 _MMIO(0x67400)
#define SPLITTER_ENABLE (1 << 31)
#define JOINER_ENABLE (1 << 30)
#define DUAL_LINK_MODE_INTERLEAVE (1 << 24)
#define DUAL_LINK_MODE_FRONTBACK (0 << 24)
#define OVERLAP_PIXELS_MASK (0xf << 16)
#define OVERLAP_PIXELS(pixels) ((pixels) << 16)
#define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
#define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
#define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0
#define DSS_CTL2 _MMIO(0x67404)
drm/i915/vdsc: Use VDSC0/VDSC1 for LEFT/RIGHT VDSC engine Drop use of LEFT/RIGHT VDSC engine and use VDSC0/VDSC1 instead. While at it, use REG_BIT macro for the bits. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241030041036.1238006-4-ankit.k.nautiyal@intel.com
2024-10-30 09:40:32 +05:30
#define VDSC0_ENABLE REG_BIT(31)
drm/i915/vdsc: Introduce 3rd VDSC engine VDSC2 Introduce the register bits to enable the 3rd DSC engine VDSC2. Add support to read/write these bits. v2: Only introduce bits that are used and update the subject and commit message. (Suraj) Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241030041036.1238006-5-ankit.k.nautiyal@intel.com
2024-10-30 09:40:33 +05:30
#define VDSC2_ENABLE REG_BIT(30)
#define SMALL_JOINER_CONFIG_3_ENGINES REG_BIT(23)
drm/i915/vdsc: Use VDSC0/VDSC1 for LEFT/RIGHT VDSC engine Drop use of LEFT/RIGHT VDSC engine and use VDSC0/VDSC1 instead. While at it, use REG_BIT macro for the bits. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241030041036.1238006-4-ankit.k.nautiyal@intel.com
2024-10-30 09:40:32 +05:30
#define VDSC1_ENABLE REG_BIT(15)
drm/i915/display: split out DSC and DSS registers Relatively few places need the DSC and DSS register definitions. Move them to intel_vdsc_regs.h. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230301151949.1591501-1-jani.nikula@intel.com
2023-03-01 17:19:49 +02:00
#define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
#define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
#define _ICL_PIPE_DSS_CTL1_PB 0x78200
#define _ICL_PIPE_DSS_CTL1_PC 0x78400
#define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_PIPE_DSS_CTL1_PB, \
_ICL_PIPE_DSS_CTL1_PC)
#define BIG_JOINER_ENABLE (1 << 29)
drm/i915: Rename bigjoiner master/slave to bigjoiner primary/secondary According to BSpec we now should call "master" pipes, "primary" pipes and "slave" pipes, should be "secondary" pipes. Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> [vsyrjala: Don't rename port sync stuff, catch a few more things] Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240603112551.6481-3-stanislav.lisovskiy@intel.com
2024-06-03 14:25:50 +03:00
#define PRIMARY_BIG_JOINER_ENABLE (1 << 28)
drm/i915/display: split out DSC and DSS registers Relatively few places need the DSC and DSS register definitions. Move them to intel_vdsc_regs.h. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230301151949.1591501-1-jani.nikula@intel.com
2023-03-01 17:19:49 +02:00
#define VGA_CENTERING_ENABLE (1 << 27)
#define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25)
#define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
#define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
drm/i915: Implement hw state readout and checks for ultrajoiner Ultrajoiner mode has some new bits and states to be read out from the hw. Lets make changes accordingly. v2: Fix checkpatch warnings. (Ankit) v3: Add separate functions for computing expected secondary_big/ultrajoiner pipes. (Ankit) v4: -Streamline the helpers for ultrajoiner. (Ville) -Add fixup to accommodate PIPED check for ultrajoiner. (Ville) -Add more Ultrajoiner drm_WARNs. (Ville) v5: Remove spurious newline. (Ville) Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240930163549.416410-6-ankit.k.nautiyal@intel.com
2024-09-30 22:05:41 +05:30
#define ULTRA_JOINER_ENABLE REG_BIT(23)
#define PRIMARY_ULTRA_JOINER_ENABLE REG_BIT(22)
drm/i915: Rename bigjoiner master/slave to bigjoiner primary/secondary According to BSpec we now should call "master" pipes, "primary" pipes and "slave" pipes, should be "secondary" pipes. Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> [vsyrjala: Don't rename port sync stuff, catch a few more things] Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240603112551.6481-3-stanislav.lisovskiy@intel.com
2024-06-03 14:25:50 +03:00
#define UNCOMPRESSED_JOINER_PRIMARY (1 << 21)
#define UNCOMPRESSED_JOINER_SECONDARY (1 << 20)
drm/i915/display: split out DSC and DSS registers Relatively few places need the DSC and DSS register definitions. Move them to intel_vdsc_regs.h. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230301151949.1591501-1-jani.nikula@intel.com
2023-03-01 17:19:49 +02:00
#define _ICL_PIPE_DSS_CTL2_PB 0x78204
#define _ICL_PIPE_DSS_CTL2_PC 0x78404
#define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_PIPE_DSS_CTL2_PB, \
_ICL_PIPE_DSS_CTL2_PC)
/* Icelake Display Stream Compression Registers */
#define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
#define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)
drm/i915/vdsc: Add function to read any PPS register Add function to read any PPS register based on the intel_dsc_pps enum provided. Add a function which will call the new pps read function and place it in crtc state. Only PPS0 and PPS1 are readout the rest of the registers will be read in upcoming patches. --v2 -Changes in read function as PPS enum is removed -Initialize pps_val as 0 in pps_read func itself [Jani] -Create a function that gets the required register and call that in the common read function [Jani] -Move the drm_WARN_ON one abstraction layer above [Jani] --v3 -Send both reg values regardless of dsc engine no [Jani] -Don't use num_vdsc_instances stick to dsc_split field [Ankit] --v4 -Manipulate the reg values instead of creating MACRO to change name of pps [Ankit] --v5 -Read dsc reg values using array rather than individual variables [Ankit] -Loop the verification of all dsc engine reads to future proof it [Ankit] -Keep the fix me comment in this patch and remove it in later one where we add other readouts [Ankit] -Add switch statement that fills in the required registers based on no of vdsc engines per pipe. --v7 -Pass no of vdsc instances from read_reg function [Ankit] -Fix issue where arrays do not get freed on return for read_and_verify func [Ankit] --v8 -Simplify reading and verifying of register and remove dynamically allocated arrays [Jani] -Remove no_ from no_vdsc_per_pipe and wherever else it applies [Ankit] --v9 -change variable name to dsc_reg_size rather than vdsc_per_pipe [Ankit] --v10 -remove switch case as we never enter case1 [Ankit] --v11 -Add _ prefix for register that are not supposed to be used directly [Jani] -Remove REG suffix from register macros [Jani] -Do not duplicate register read [Jani] --v12 -Use vdsc_per_pipe rather than array size of dsc_reg [Jani] Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230828054300.560559-5-suraj.kandpal@intel.com
2023-08-28 11:12:57 +05:30
#define _DSCA_PPS_0 0x6B200
#define _DSCC_PPS_0 0x6BA00
drm/i915/dsc: Fix the macro that calculates DSCC_/DSCA_ PPS reg address Commit bd077259d0a9 ("drm/i915/vdsc: Add function to read any PPS register") defines a new macro to calculate the DSC PPS register addresses with PPS number as an input. This macro correctly calculates the addresses till PPS 11 since the addresses increment by 4. So in that case the following macro works correctly to give correct register address: _MMIO(_DSCA_PPS_0 + (pps) * 4) However after PPS 11, the register address for PPS 12 increments by 12 because of RC Buffer memory allocation in between. Because of this discontinuity in the address space, the macro calculates wrong addresses for PPS 12 - 16 resulting into incorrect DSC PPS parameter value read/writes causing DSC corruption. This fixes it by correcting this macro to add the offset of 12 for PPS >=12. v3: Add correct paranthesis for pps argument (Jani Nikula) Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/10172 Fixes: bd077259d0a9 ("drm/i915/vdsc: Add function to read any PPS register") Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Cc: Animesh Manna <animesh.manna@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Sean Paul <sean@poorly.run> Cc: Drew Davenport <ddavenport@chromium.org> Signed-off-by: Manasi Navare <navaremanasi@chromium.org> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240205204619.1991673-1-navaremanasi@chromium.org
2024-02-05 20:46:19 +00:00
#define DSCA_PPS(pps) _MMIO(_DSCA_PPS_0 + ((pps) < 12 ? (pps) : (pps) + 12) * 4)
#define DSCC_PPS(pps) _MMIO(_DSCC_PPS_0 + ((pps) < 12 ? (pps) : (pps) + 12) * 4)
drm/i915/display: split out DSC and DSS registers Relatively few places need the DSC and DSS register definitions. Move them to intel_vdsc_regs.h. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230301151949.1591501-1-jani.nikula@intel.com
2023-03-01 17:19:49 +02:00
#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270
#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370
drm/i915/vdsc: Add support for read/write PPS for 3rd DSC engine With BMG each pipe has 3 DSC engines, so add bits to read/write the PPS registers for the 3rd DSC engine Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241030041036.1238006-6-ankit.k.nautiyal@intel.com
2024-10-30 09:40:34 +05:30
#define _BMG_DSC2_PICTURE_PARAMETER_SET_0_PB 0x78970
drm/i915/display: split out DSC and DSS registers Relatively few places need the DSC and DSS register definitions. Move them to intel_vdsc_regs.h. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230301151949.1591501-1-jani.nikula@intel.com
2023-03-01 17:19:49 +02:00
#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470
#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570
drm/i915/vdsc: Add support for read/write PPS for 3rd DSC engine With BMG each pipe has 3 DSC engines, so add bits to read/write the PPS registers for the 3rd DSC engine Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241030041036.1238006-6-ankit.k.nautiyal@intel.com
2024-10-30 09:40:34 +05:30
#define _BMG_DSC2_PICTURE_PARAMETER_SET_0_PC 0x78A70
drm/i915/display: split out DSC and DSS registers Relatively few places need the DSC and DSS register definitions. Move them to intel_vdsc_regs.h. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230301151949.1591501-1-jani.nikula@intel.com
2023-03-01 17:19:49 +02:00
#define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
_ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
#define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
_ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
drm/i915/vdsc: Add function to read any PPS register Add function to read any PPS register based on the intel_dsc_pps enum provided. Add a function which will call the new pps read function and place it in crtc state. Only PPS0 and PPS1 are readout the rest of the registers will be read in upcoming patches. --v2 -Changes in read function as PPS enum is removed -Initialize pps_val as 0 in pps_read func itself [Jani] -Create a function that gets the required register and call that in the common read function [Jani] -Move the drm_WARN_ON one abstraction layer above [Jani] --v3 -Send both reg values regardless of dsc engine no [Jani] -Don't use num_vdsc_instances stick to dsc_split field [Ankit] --v4 -Manipulate the reg values instead of creating MACRO to change name of pps [Ankit] --v5 -Read dsc reg values using array rather than individual variables [Ankit] -Loop the verification of all dsc engine reads to future proof it [Ankit] -Keep the fix me comment in this patch and remove it in later one where we add other readouts [Ankit] -Add switch statement that fills in the required registers based on no of vdsc engines per pipe. --v7 -Pass no of vdsc instances from read_reg function [Ankit] -Fix issue where arrays do not get freed on return for read_and_verify func [Ankit] --v8 -Simplify reading and verifying of register and remove dynamically allocated arrays [Jani] -Remove no_ from no_vdsc_per_pipe and wherever else it applies [Ankit] --v9 -change variable name to dsc_reg_size rather than vdsc_per_pipe [Ankit] --v10 -remove switch case as we never enter case1 [Ankit] --v11 -Add _ prefix for register that are not supposed to be used directly [Jani] -Remove REG suffix from register macros [Jani] -Do not duplicate register read [Jani] --v12 -Use vdsc_per_pipe rather than array size of dsc_reg [Jani] Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230828054300.560559-5-suraj.kandpal@intel.com
2023-08-28 11:12:57 +05:30
#define _ICL_DSC0_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \
_ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
_ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
#define _ICL_DSC1_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \
_ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
_ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
drm/i915/vdsc: Add support for read/write PPS for 3rd DSC engine With BMG each pipe has 3 DSC engines, so add bits to read/write the PPS registers for the 3rd DSC engine Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241030041036.1238006-6-ankit.k.nautiyal@intel.com
2024-10-30 09:40:34 +05:30
#define _BMG_DSC2_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \
_BMG_DSC2_PICTURE_PARAMETER_SET_0_PB, \
_BMG_DSC2_PICTURE_PARAMETER_SET_0_PC)
drm/i915/vdsc: Add function to read any PPS register Add function to read any PPS register based on the intel_dsc_pps enum provided. Add a function which will call the new pps read function and place it in crtc state. Only PPS0 and PPS1 are readout the rest of the registers will be read in upcoming patches. --v2 -Changes in read function as PPS enum is removed -Initialize pps_val as 0 in pps_read func itself [Jani] -Create a function that gets the required register and call that in the common read function [Jani] -Move the drm_WARN_ON one abstraction layer above [Jani] --v3 -Send both reg values regardless of dsc engine no [Jani] -Don't use num_vdsc_instances stick to dsc_split field [Ankit] --v4 -Manipulate the reg values instead of creating MACRO to change name of pps [Ankit] --v5 -Read dsc reg values using array rather than individual variables [Ankit] -Loop the verification of all dsc engine reads to future proof it [Ankit] -Keep the fix me comment in this patch and remove it in later one where we add other readouts [Ankit] -Add switch statement that fills in the required registers based on no of vdsc engines per pipe. --v7 -Pass no of vdsc instances from read_reg function [Ankit] -Fix issue where arrays do not get freed on return for read_and_verify func [Ankit] --v8 -Simplify reading and verifying of register and remove dynamically allocated arrays [Jani] -Remove no_ from no_vdsc_per_pipe and wherever else it applies [Ankit] --v9 -change variable name to dsc_reg_size rather than vdsc_per_pipe [Ankit] --v10 -remove switch case as we never enter case1 [Ankit] --v11 -Add _ prefix for register that are not supposed to be used directly [Jani] -Remove REG suffix from register macros [Jani] -Do not duplicate register read [Jani] --v12 -Use vdsc_per_pipe rather than array size of dsc_reg [Jani] Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230828054300.560559-5-suraj.kandpal@intel.com
2023-08-28 11:12:57 +05:30
#define ICL_DSC0_PPS(pipe, pps) _MMIO(_ICL_DSC0_PPS_0(pipe) + ((pps) * 4))
#define ICL_DSC1_PPS(pipe, pps) _MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4))
drm/i915/vdsc: Add support for read/write PPS for 3rd DSC engine With BMG each pipe has 3 DSC engines, so add bits to read/write the PPS registers for the 3rd DSC engine Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241030041036.1238006-6-ankit.k.nautiyal@intel.com
2024-10-30 09:40:34 +05:30
#define BMG_DSC2_PPS(pipe, pps) _MMIO(_BMG_DSC2_PPS_0(pipe) + ((pps) * 4))
drm/i915/vdsc: Remove unused dsc registers Now that we have macros that can fetch dsc register values based on pipe and pps parameters we can go ahead and remove all the unused register. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230828054300.560559-7-suraj.kandpal@intel.com
2023-08-28 11:12:59 +05:30
drm/i915/dsc: clean up pps comments Unify comments to be the simple "PPS n" instead of all sorts of variants. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/915970973ef117fc8d47fbc57e8fa296235ad3e3.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:25 +03:00
/* PPS 0 */
drm/i915/dsc: use REG_BIT, REG_GENMASK, and friends for PPS0 and PPS1 Use the register helper macros for PPS0 and PPS1 register contents. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/0dfebe37a391a5ceb8bfae8e16383f1e5aef815d.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:27 +03:00
#define DSC_PPS0_NATIVE_422_ENABLE REG_BIT(23)
#define DSC_PPS0_NATIVE_420_ENABLE REG_BIT(22)
#define DSC_PPS0_ALT_ICH_SEL REG_BIT(20)
#define DSC_PPS0_VBR_ENABLE REG_BIT(19)
#define DSC_PPS0_422_ENABLE REG_BIT(18)
#define DSC_PPS0_COLOR_SPACE_CONVERSION REG_BIT(17)
#define DSC_PPS0_BLOCK_PREDICTION REG_BIT(16)
drm/i915/dsc: add the PPS number to the register content macros Improve clarity by specifying the PPS number in the register content macros. It's easier to notice if macros are being used for the wrong register. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/58de57b04ad2da5207f52c56c9e40663aaf16173.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:26 +03:00
#define DSC_PPS0_LINE_BUF_DEPTH_MASK REG_GENMASK(15, 12)
drm/i915/dsc: use REG_BIT, REG_GENMASK, and friends for PPS0 and PPS1 Use the register helper macros for PPS0 and PPS1 register contents. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/0dfebe37a391a5ceb8bfae8e16383f1e5aef815d.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:27 +03:00
#define DSC_PPS0_LINE_BUF_DEPTH(depth) REG_FIELD_PREP(DSC_PPS0_LINE_BUF_DEPTH_MASK, depth)
drm/i915/dsc: add the PPS number to the register content macros Improve clarity by specifying the PPS number in the register content macros. It's easier to notice if macros are being used for the wrong register. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/58de57b04ad2da5207f52c56c9e40663aaf16173.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:26 +03:00
#define DSC_PPS0_BPC_MASK REG_GENMASK(11, 8)
drm/i915/dsc: use REG_BIT, REG_GENMASK, and friends for PPS0 and PPS1 Use the register helper macros for PPS0 and PPS1 register contents. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/0dfebe37a391a5ceb8bfae8e16383f1e5aef815d.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:27 +03:00
#define DSC_PPS0_BPC(bpc) REG_FIELD_PREP(DSC_PPS0_BPC_MASK, bpc)
#define DSC_PPS0_VER_MINOR_MASK REG_GENMASK(7, 4)
#define DSC_PPS0_VER_MINOR(minor) REG_FIELD_PREP(DSC_PPS0_VER_MINOR_MASK, minor)
#define DSC_PPS0_VER_MAJOR_MASK REG_GENMASK(3, 0)
#define DSC_PPS0_VER_MAJOR(major) REG_FIELD_PREP(DSC_PPS0_VER_MAJOR_MASK, major)
drm/i915/display: split out DSC and DSS registers Relatively few places need the DSC and DSS register definitions. Move them to intel_vdsc_regs.h. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230301151949.1591501-1-jani.nikula@intel.com
2023-03-01 17:19:49 +02:00
drm/i915/dsc: clean up pps comments Unify comments to be the simple "PPS n" instead of all sorts of variants. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/915970973ef117fc8d47fbc57e8fa296235ad3e3.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:25 +03:00
/* PPS 1 */
drm/i915/dsc: use REG_BIT, REG_GENMASK, and friends for PPS0 and PPS1 Use the register helper macros for PPS0 and PPS1 register contents. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/0dfebe37a391a5ceb8bfae8e16383f1e5aef815d.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:27 +03:00
#define DSC_PPS1_BPP_MASK REG_GENMASK(9, 0)
#define DSC_PPS1_BPP(bpp) REG_FIELD_PREP(DSC_PPS1_BPP_MASK, bpp)
drm/i915/display: split out DSC and DSS registers Relatively few places need the DSC and DSS register definitions. Move them to intel_vdsc_regs.h. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230301151949.1591501-1-jani.nikula@intel.com
2023-03-01 17:19:49 +02:00
drm/i915/dsc: clean up pps comments Unify comments to be the simple "PPS n" instead of all sorts of variants. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/915970973ef117fc8d47fbc57e8fa296235ad3e3.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:25 +03:00
/* PPS 2 */
drm/i915/dsc: add the PPS number to the register content macros Improve clarity by specifying the PPS number in the register content macros. It's easier to notice if macros are being used for the wrong register. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/58de57b04ad2da5207f52c56c9e40663aaf16173.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:26 +03:00
#define DSC_PPS2_PIC_WIDTH_MASK REG_GENMASK(31, 16)
#define DSC_PPS2_PIC_HEIGHT_MASK REG_GENMASK(15, 0)
#define DSC_PPS2_PIC_WIDTH(pic_width) REG_FIELD_PREP(DSC_PPS2_PIC_WIDTH_MASK, pic_width)
#define DSC_PPS2_PIC_HEIGHT(pic_height) REG_FIELD_PREP(DSC_PPS2_PIC_HEIGHT_MASK, pic_height)
drm/i915/display: split out DSC and DSS registers Relatively few places need the DSC and DSS register definitions. Move them to intel_vdsc_regs.h. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230301151949.1591501-1-jani.nikula@intel.com
2023-03-01 17:19:49 +02:00
drm/i915/dsc: clean up pps comments Unify comments to be the simple "PPS n" instead of all sorts of variants. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/915970973ef117fc8d47fbc57e8fa296235ad3e3.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:25 +03:00
/* PPS 3 */
drm/i915/dsc: add the PPS number to the register content macros Improve clarity by specifying the PPS number in the register content macros. It's easier to notice if macros are being used for the wrong register. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/58de57b04ad2da5207f52c56c9e40663aaf16173.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:26 +03:00
#define DSC_PPS3_SLICE_WIDTH_MASK REG_GENMASK(31, 16)
#define DSC_PPS3_SLICE_HEIGHT_MASK REG_GENMASK(15, 0)
#define DSC_PPS3_SLICE_WIDTH(slice_width) REG_FIELD_PREP(DSC_PPS3_SLICE_WIDTH_MASK, slice_width)
#define DSC_PPS3_SLICE_HEIGHT(slice_height) REG_FIELD_PREP(DSC_PPS3_SLICE_HEIGHT_MASK, slice_height)
drm/i915/display: split out DSC and DSS registers Relatively few places need the DSC and DSS register definitions. Move them to intel_vdsc_regs.h. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230301151949.1591501-1-jani.nikula@intel.com
2023-03-01 17:19:49 +02:00
drm/i915/dsc: clean up pps comments Unify comments to be the simple "PPS n" instead of all sorts of variants. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/915970973ef117fc8d47fbc57e8fa296235ad3e3.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:25 +03:00
/* PPS 4 */
drm/i915/dsc: add the PPS number to the register content macros Improve clarity by specifying the PPS number in the register content macros. It's easier to notice if macros are being used for the wrong register. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/58de57b04ad2da5207f52c56c9e40663aaf16173.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:26 +03:00
#define DSC_PPS4_INITIAL_DEC_DELAY_MASK REG_GENMASK(31, 16)
#define DSC_PPS4_INITIAL_XMIT_DELAY_MASK REG_GENMASK(9, 0)
#define DSC_PPS4_INITIAL_DEC_DELAY(dec_delay) REG_FIELD_PREP(DSC_PPS4_INITIAL_DEC_DELAY_MASK, \
drm/i915/vdsc: Refactor dsc register field macro This patch refactors dsc register related macros that prepares the values to be written in the register. The current bit shifting looks bad and going forward will not serve our purpose to readout dsc register field values the change was suggested by Jani Nikula. Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230828054300.560559-2-suraj.kandpal@intel.com
2023-08-28 11:12:54 +05:30
dec_delay)
drm/i915/dsc: add the PPS number to the register content macros Improve clarity by specifying the PPS number in the register content macros. It's easier to notice if macros are being used for the wrong register. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/58de57b04ad2da5207f52c56c9e40663aaf16173.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:26 +03:00
#define DSC_PPS4_INITIAL_XMIT_DELAY(xmit_delay) REG_FIELD_PREP(DSC_PPS4_INITIAL_XMIT_DELAY_MASK, \
xmit_delay)
drm/i915/display: split out DSC and DSS registers Relatively few places need the DSC and DSS register definitions. Move them to intel_vdsc_regs.h. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230301151949.1591501-1-jani.nikula@intel.com
2023-03-01 17:19:49 +02:00
drm/i915/dsc: clean up pps comments Unify comments to be the simple "PPS n" instead of all sorts of variants. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/915970973ef117fc8d47fbc57e8fa296235ad3e3.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:25 +03:00
/* PPS 5 */
drm/i915/dsc: add the PPS number to the register content macros Improve clarity by specifying the PPS number in the register content macros. It's easier to notice if macros are being used for the wrong register. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/58de57b04ad2da5207f52c56c9e40663aaf16173.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:26 +03:00
#define DSC_PPS5_SCALE_DEC_INT_MASK REG_GENMASK(27, 16)
#define DSC_PPS5_SCALE_INC_INT_MASK REG_GENMASK(15, 0)
#define DSC_PPS5_SCALE_DEC_INT(scale_dec) REG_FIELD_PREP(DSC_PPS5_SCALE_DEC_INT_MASK, scale_dec)
#define DSC_PPS5_SCALE_INC_INT(scale_inc) REG_FIELD_PREP(DSC_PPS5_SCALE_INC_INT_MASK, scale_inc)
drm/i915/display: split out DSC and DSS registers Relatively few places need the DSC and DSS register definitions. Move them to intel_vdsc_regs.h. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230301151949.1591501-1-jani.nikula@intel.com
2023-03-01 17:19:49 +02:00
drm/i915/dsc: clean up pps comments Unify comments to be the simple "PPS n" instead of all sorts of variants. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/915970973ef117fc8d47fbc57e8fa296235ad3e3.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:25 +03:00
/* PPS 6 */
drm/i915/dsc: add the PPS number to the register content macros Improve clarity by specifying the PPS number in the register content macros. It's easier to notice if macros are being used for the wrong register. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/58de57b04ad2da5207f52c56c9e40663aaf16173.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:26 +03:00
#define DSC_PPS6_FLATNESS_MAX_QP_MASK REG_GENMASK(28, 24)
#define DSC_PPS6_FLATNESS_MIN_QP_MASK REG_GENMASK(20, 16)
#define DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK REG_GENMASK(12, 8)
#define DSC_PPS6_INITIAL_SCALE_VALUE_MASK REG_GENMASK(5, 0)
#define DSC_PPS6_FLATNESS_MAX_QP(max_qp) REG_FIELD_PREP(DSC_PPS6_FLATNESS_MAX_QP_MASK, max_qp)
#define DSC_PPS6_FLATNESS_MIN_QP(min_qp) REG_FIELD_PREP(DSC_PPS6_FLATNESS_MIN_QP_MASK, min_qp)
#define DSC_PPS6_FIRST_LINE_BPG_OFFSET(offset) REG_FIELD_PREP(DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK, \
offset)
#define DSC_PPS6_INITIAL_SCALE_VALUE(value) REG_FIELD_PREP(DSC_PPS6_INITIAL_SCALE_VALUE_MASK, \
drm/i915/vdsc: Refactor dsc register field macro This patch refactors dsc register related macros that prepares the values to be written in the register. The current bit shifting looks bad and going forward will not serve our purpose to readout dsc register field values the change was suggested by Jani Nikula. Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230828054300.560559-2-suraj.kandpal@intel.com
2023-08-28 11:12:54 +05:30
value)
drm/i915/display: split out DSC and DSS registers Relatively few places need the DSC and DSS register definitions. Move them to intel_vdsc_regs.h. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230301151949.1591501-1-jani.nikula@intel.com
2023-03-01 17:19:49 +02:00
drm/i915/dsc: clean up pps comments Unify comments to be the simple "PPS n" instead of all sorts of variants. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/915970973ef117fc8d47fbc57e8fa296235ad3e3.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:25 +03:00
/* PPS 7 */
drm/i915/dsc: add the PPS number to the register content macros Improve clarity by specifying the PPS number in the register content macros. It's easier to notice if macros are being used for the wrong register. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/58de57b04ad2da5207f52c56c9e40663aaf16173.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:26 +03:00
#define DSC_PPS7_NFL_BPG_OFFSET_MASK REG_GENMASK(31, 16)
#define DSC_PPS7_SLICE_BPG_OFFSET_MASK REG_GENMASK(15, 0)
#define DSC_PPS7_NFL_BPG_OFFSET(bpg_offset) REG_FIELD_PREP(DSC_PPS7_NFL_BPG_OFFSET_MASK, bpg_offset)
#define DSC_PPS7_SLICE_BPG_OFFSET(bpg_offset) REG_FIELD_PREP(DSC_PPS7_SLICE_BPG_OFFSET_MASK, \
drm/i915/vdsc: Refactor dsc register field macro This patch refactors dsc register related macros that prepares the values to be written in the register. The current bit shifting looks bad and going forward will not serve our purpose to readout dsc register field values the change was suggested by Jani Nikula. Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230828054300.560559-2-suraj.kandpal@intel.com
2023-08-28 11:12:54 +05:30
bpg_offset)
drm/i915/dsc: clean up pps comments Unify comments to be the simple "PPS n" instead of all sorts of variants. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/915970973ef117fc8d47fbc57e8fa296235ad3e3.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:25 +03:00
/* PPS 8 */
drm/i915/dsc: add the PPS number to the register content macros Improve clarity by specifying the PPS number in the register content macros. It's easier to notice if macros are being used for the wrong register. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/58de57b04ad2da5207f52c56c9e40663aaf16173.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:26 +03:00
#define DSC_PPS8_INITIAL_OFFSET_MASK REG_GENMASK(31, 16)
#define DSC_PPS8_FINAL_OFFSET_MASK REG_GENMASK(15, 0)
#define DSC_PPS8_INITIAL_OFFSET(initial_offset) REG_FIELD_PREP(DSC_PPS8_INITIAL_OFFSET_MASK, \
initial_offset)
#define DSC_PPS8_FINAL_OFFSET(final_offset) REG_FIELD_PREP(DSC_PPS8_FINAL_OFFSET_MASK, \
drm/i915/vdsc: Refactor dsc register field macro This patch refactors dsc register related macros that prepares the values to be written in the register. The current bit shifting looks bad and going forward will not serve our purpose to readout dsc register field values the change was suggested by Jani Nikula. Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230828054300.560559-2-suraj.kandpal@intel.com
2023-08-28 11:12:54 +05:30
final_offset)
drm/i915/display: split out DSC and DSS registers Relatively few places need the DSC and DSS register definitions. Move them to intel_vdsc_regs.h. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230301151949.1591501-1-jani.nikula@intel.com
2023-03-01 17:19:49 +02:00
drm/i915/dsc: clean up pps comments Unify comments to be the simple "PPS n" instead of all sorts of variants. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/915970973ef117fc8d47fbc57e8fa296235ad3e3.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:25 +03:00
/* PPS 9 */
drm/i915/dsc: add the PPS number to the register content macros Improve clarity by specifying the PPS number in the register content macros. It's easier to notice if macros are being used for the wrong register. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/58de57b04ad2da5207f52c56c9e40663aaf16173.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:26 +03:00
#define DSC_PPS9_RC_EDGE_FACTOR_MASK REG_GENMASK(19, 16)
#define DSC_PPS9_RC_MODEL_SIZE_MASK REG_GENMASK(15, 0)
#define DSC_PPS9_RC_EDGE_FACTOR(rc_edge_fact) REG_FIELD_PREP(DSC_PPS9_RC_EDGE_FACTOR_MASK, \
drm/i915/vdsc: Refactor dsc register field macro This patch refactors dsc register related macros that prepares the values to be written in the register. The current bit shifting looks bad and going forward will not serve our purpose to readout dsc register field values the change was suggested by Jani Nikula. Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230828054300.560559-2-suraj.kandpal@intel.com
2023-08-28 11:12:54 +05:30
rc_edge_fact)
drm/i915/dsc: add the PPS number to the register content macros Improve clarity by specifying the PPS number in the register content macros. It's easier to notice if macros are being used for the wrong register. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/58de57b04ad2da5207f52c56c9e40663aaf16173.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:26 +03:00
#define DSC_PPS9_RC_MODEL_SIZE(rc_model_size) REG_FIELD_PREP(DSC_PPS9_RC_MODEL_SIZE_MASK, \
drm/i915/vdsc: Refactor dsc register field macro This patch refactors dsc register related macros that prepares the values to be written in the register. The current bit shifting looks bad and going forward will not serve our purpose to readout dsc register field values the change was suggested by Jani Nikula. Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230828054300.560559-2-suraj.kandpal@intel.com
2023-08-28 11:12:54 +05:30
rc_model_size)
drm/i915/display: split out DSC and DSS registers Relatively few places need the DSC and DSS register definitions. Move them to intel_vdsc_regs.h. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230301151949.1591501-1-jani.nikula@intel.com
2023-03-01 17:19:49 +02:00
drm/i915/dsc: clean up pps comments Unify comments to be the simple "PPS n" instead of all sorts of variants. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/915970973ef117fc8d47fbc57e8fa296235ad3e3.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:25 +03:00
/* PPS 10 */
drm/i915/dsc: add the PPS number to the register content macros Improve clarity by specifying the PPS number in the register content macros. It's easier to notice if macros are being used for the wrong register. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/58de57b04ad2da5207f52c56c9e40663aaf16173.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:26 +03:00
#define DSC_PPS10_RC_TGT_OFF_LOW_MASK REG_GENMASK(23, 20)
#define DSC_PPS10_RC_TGT_OFF_HIGH_MASK REG_GENMASK(19, 16)
#define DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK REG_GENMASK(12, 8)
#define DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK REG_GENMASK(4, 0)
#define DSC_PPS10_RC_TARGET_OFF_LOW(rc_tgt_off_low) REG_FIELD_PREP(DSC_PPS10_RC_TGT_OFF_LOW_MASK, \
drm/i915/vdsc: Refactor dsc register field macro This patch refactors dsc register related macros that prepares the values to be written in the register. The current bit shifting looks bad and going forward will not serve our purpose to readout dsc register field values the change was suggested by Jani Nikula. Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230828054300.560559-2-suraj.kandpal@intel.com
2023-08-28 11:12:54 +05:30
rc_tgt_off_low)
drm/i915/dsc: add the PPS number to the register content macros Improve clarity by specifying the PPS number in the register content macros. It's easier to notice if macros are being used for the wrong register. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/58de57b04ad2da5207f52c56c9e40663aaf16173.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:26 +03:00
#define DSC_PPS10_RC_TARGET_OFF_HIGH(rc_tgt_off_high) REG_FIELD_PREP(DSC_PPS10_RC_TGT_OFF_HIGH_MASK, \
drm/i915/vdsc: Refactor dsc register field macro This patch refactors dsc register related macros that prepares the values to be written in the register. The current bit shifting looks bad and going forward will not serve our purpose to readout dsc register field values the change was suggested by Jani Nikula. Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230828054300.560559-2-suraj.kandpal@intel.com
2023-08-28 11:12:54 +05:30
rc_tgt_off_high)
drm/i915/dsc: add the PPS number to the register content macros Improve clarity by specifying the PPS number in the register content macros. It's easier to notice if macros are being used for the wrong register. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/58de57b04ad2da5207f52c56c9e40663aaf16173.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:26 +03:00
#define DSC_PPS10_RC_QUANT_INC_LIMIT1(lim) REG_FIELD_PREP(DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK, lim)
#define DSC_PPS10_RC_QUANT_INC_LIMIT0(lim) REG_FIELD_PREP(DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK, lim)
drm/i915/display: split out DSC and DSS registers Relatively few places need the DSC and DSS register definitions. Move them to intel_vdsc_regs.h. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230301151949.1591501-1-jani.nikula@intel.com
2023-03-01 17:19:49 +02:00
drm/i915/dsc: clean up pps comments Unify comments to be the simple "PPS n" instead of all sorts of variants. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/915970973ef117fc8d47fbc57e8fa296235ad3e3.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:25 +03:00
/* PPS 16 */
drm/i915/dsc: add the PPS number to the register content macros Improve clarity by specifying the PPS number in the register content macros. It's easier to notice if macros are being used for the wrong register. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/58de57b04ad2da5207f52c56c9e40663aaf16173.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:26 +03:00
#define DSC_PPS16_SLICE_ROW_PR_FRME_MASK REG_GENMASK(31, 20)
#define DSC_PPS16_SLICE_PER_LINE_MASK REG_GENMASK(18, 16)
#define DSC_PPS16_SLICE_CHUNK_SIZE_MASK REG_GENMASK(15, 0)
#define DSC_PPS16_SLICE_ROW_PER_FRAME(slice_row_per_frame) REG_FIELD_PREP(DSC_PPS16_SLICE_ROW_PR_FRME_MASK, \
slice_row_per_frame)
#define DSC_PPS16_SLICE_PER_LINE(slice_per_line) REG_FIELD_PREP(DSC_PPS16_SLICE_PER_LINE_MASK, \
slice_per_line)
#define DSC_PPS16_SLICE_CHUNK_SIZE(slice_chunk_size) REG_FIELD_PREP(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, \
slice_chunk_size)
drm/i915/display: split out DSC and DSS registers Relatively few places need the DSC and DSS register definitions. Move them to intel_vdsc_regs.h. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230301151949.1591501-1-jani.nikula@intel.com
2023-03-01 17:19:49 +02:00
drm/i915/dsc: clean up pps comments Unify comments to be the simple "PPS n" instead of all sorts of variants. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/915970973ef117fc8d47fbc57e8fa296235ad3e3.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:25 +03:00
/* PPS 17 (MTL+) */
drm/i915/dsc: add the PPS number to the register content macros Improve clarity by specifying the PPS number in the register content macros. It's easier to notice if macros are being used for the wrong register. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/58de57b04ad2da5207f52c56c9e40663aaf16173.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:26 +03:00
#define DSC_PPS17_SL_BPG_OFFSET_MASK REG_GENMASK(31, 27)
#define DSC_PPS17_SL_BPG_OFFSET(offset) REG_FIELD_PREP(DSC_PPS17_SL_BPG_OFFSET_MASK, offset)
drm/i915/vdsc: Remove unused dsc registers Now that we have macros that can fetch dsc register values based on pipe and pps parameters we can go ahead and remove all the unused register. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230828054300.560559-7-suraj.kandpal@intel.com
2023-08-28 11:12:59 +05:30
drm/i915/dsc: clean up pps comments Unify comments to be the simple "PPS n" instead of all sorts of variants. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/915970973ef117fc8d47fbc57e8fa296235ad3e3.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:25 +03:00
/* PPS 18 (MTL+) */
drm/i915/dsc: add the PPS number to the register content macros Improve clarity by specifying the PPS number in the register content macros. It's easier to notice if macros are being used for the wrong register. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/58de57b04ad2da5207f52c56c9e40663aaf16173.1693933849.git.jani.nikula@intel.com
2023-09-05 20:11:26 +03:00
#define DSC_PPS18_NSL_BPG_OFFSET_MASK REG_GENMASK(31, 16)
#define DSC_PPS18_SL_OFFSET_ADJ_MASK REG_GENMASK(15, 0)
#define DSC_PPS18_NSL_BPG_OFFSET(offset) REG_FIELD_PREP(DSC_PPS18_NSL_BPG_OFFSET_MASK, offset)
#define DSC_PPS18_SL_OFFSET_ADJ(offset) REG_FIELD_PREP(DSC_PPS18_SL_OFFSET_ADJ_MASK, offset)
drm/i915/vdsc: Remove unused dsc registers Now that we have macros that can fetch dsc register values based on pipe and pps parameters we can go ahead and remove all the unused register. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230828054300.560559-7-suraj.kandpal@intel.com
2023-08-28 11:12:59 +05:30
drm/i915/display: split out DSC and DSS registers Relatively few places need the DSC and DSS register definitions. Move them to intel_vdsc_regs.h. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230301151949.1591501-1-jani.nikula@intel.com
2023-03-01 17:19:49 +02:00
/* Icelake Rate Control Buffer Threshold Registers */
#define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)
#define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4)
#define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30)
#define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4)
#define _ICL_DSC0_RC_BUF_THRESH_0_PB (0x78254)
#define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB (0x78254 + 4)
#define _ICL_DSC1_RC_BUF_THRESH_0_PB (0x78354)
#define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB (0x78354 + 4)
#define _ICL_DSC0_RC_BUF_THRESH_0_PC (0x78454)
#define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC (0x78454 + 4)
#define _ICL_DSC1_RC_BUF_THRESH_0_PC (0x78554)
#define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC (0x78554 + 4)
#define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC0_RC_BUF_THRESH_0_PB, \
_ICL_DSC0_RC_BUF_THRESH_0_PC)
#define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \
_ICL_DSC0_RC_BUF_THRESH_0_UDW_PC)
#define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC1_RC_BUF_THRESH_0_PB, \
_ICL_DSC1_RC_BUF_THRESH_0_PC)
#define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \
_ICL_DSC1_RC_BUF_THRESH_0_UDW_PC)
#define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238)
#define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4)
#define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38)
#define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4)
#define _ICL_DSC0_RC_BUF_THRESH_1_PB (0x7825C)
#define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB (0x7825C + 4)
#define _ICL_DSC1_RC_BUF_THRESH_1_PB (0x7835C)
#define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB (0x7835C + 4)
#define _ICL_DSC0_RC_BUF_THRESH_1_PC (0x7845C)
#define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC (0x7845C + 4)
#define _ICL_DSC1_RC_BUF_THRESH_1_PC (0x7855C)
#define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC (0x7855C + 4)
#define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC0_RC_BUF_THRESH_1_PB, \
_ICL_DSC0_RC_BUF_THRESH_1_PC)
#define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \
_ICL_DSC0_RC_BUF_THRESH_1_UDW_PC)
#define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC1_RC_BUF_THRESH_1_PB, \
_ICL_DSC1_RC_BUF_THRESH_1_PC)
#define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
_ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
/* Icelake DSC Rate Control Range Parameter Registers */
#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
#define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)
#define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40)
#define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4)
#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208)
#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4)
#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308)
#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4)
#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408)
#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4)
#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508)
#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4)
#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
_ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
_ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
_ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
_ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
#define RC_BPG_OFFSET_SHIFT 10
#define RC_MAX_QP_SHIFT 5
#define RC_MIN_QP_SHIFT 0
#define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)
#define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)
#define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)
#define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4)
#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210)
#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4)
#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310)
#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4)
#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410)
#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4)
#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510)
#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4)
#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
_ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
_ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
_ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
_ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
#define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250)
#define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4)
#define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50)
#define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4)
#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218)
#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4)
#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318)
#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4)
#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418)
#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4)
#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518)
#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4)
#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
_ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
_ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
_ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
_ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
#define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258)
#define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4)
#define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58)
#define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4)
#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220)
#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4)
#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320)
#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4)
#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420)
#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4)
#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520)
#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4)
#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
_ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
_ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
_ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
_ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
_ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
#endif /* __INTEL_VDSC_REGS_H__ */
Reference in a new issue Copy permalink