mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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258 lines
10 KiB
C
258 lines
10 KiB
C
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/* SPDX-License-Identifier: MIT */
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/* Copyright © 2024 Intel Corporation */
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#ifndef __I9XX_WM_REGS_H__
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#define __I9XX_WM_REGS_H__
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#include "intel_display_reg_defs.h"
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#define DSPARB(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
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#define DSPARB_CSTART_MASK (0x7f << 7)
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#define DSPARB_CSTART_SHIFT 7
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#define DSPARB_BSTART_MASK (0x7f)
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#define DSPARB_BSTART_SHIFT 0
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#define DSPARB_BEND_SHIFT 9 /* on 855 */
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#define DSPARB_AEND_SHIFT 0
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#define DSPARB_SPRITEA_SHIFT_VLV 0
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#define DSPARB_SPRITEA_MASK_VLV (0xff << 0)
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#define DSPARB_SPRITEB_SHIFT_VLV 8
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#define DSPARB_SPRITEB_MASK_VLV (0xff << 8)
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#define DSPARB_SPRITEC_SHIFT_VLV 16
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#define DSPARB_SPRITEC_MASK_VLV (0xff << 16)
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#define DSPARB_SPRITED_SHIFT_VLV 24
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#define DSPARB_SPRITED_MASK_VLV (0xff << 24)
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#define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
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#define DSPARB_SPRITEA_HI_SHIFT_VLV 0
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#define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0)
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#define DSPARB_SPRITEB_HI_SHIFT_VLV 4
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#define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4)
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#define DSPARB_SPRITEC_HI_SHIFT_VLV 8
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#define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8)
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#define DSPARB_SPRITED_HI_SHIFT_VLV 12
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#define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12)
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#define DSPARB_SPRITEE_HI_SHIFT_VLV 16
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#define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16)
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#define DSPARB_SPRITEF_HI_SHIFT_VLV 20
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#define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20)
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#define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
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#define DSPARB_SPRITEE_SHIFT_VLV 0
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#define DSPARB_SPRITEE_MASK_VLV (0xff << 0)
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#define DSPARB_SPRITEF_SHIFT_VLV 8
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#define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
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/* pnv/gen4/g4x/vlv/chv */
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#define DSPFW1(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
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#define DSPFW_SR_SHIFT 23
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#define DSPFW_SR_MASK (0x1ff << 23)
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#define DSPFW_CURSORB_SHIFT 16
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#define DSPFW_CURSORB_MASK (0x3f << 16)
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#define DSPFW_PLANEB_SHIFT 8
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#define DSPFW_PLANEB_MASK (0x7f << 8)
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#define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */
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#define DSPFW_PLANEA_SHIFT 0
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#define DSPFW_PLANEA_MASK (0x7f << 0)
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#define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */
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#define DSPFW2(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
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#define DSPFW_FBC_SR_EN (1 << 31) /* g4x */
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#define DSPFW_FBC_SR_SHIFT 28
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#define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */
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#define DSPFW_FBC_HPLL_SR_SHIFT 24
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#define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */
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#define DSPFW_SPRITEB_SHIFT (16)
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#define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */
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#define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */
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#define DSPFW_CURSORA_SHIFT 8
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#define DSPFW_CURSORA_MASK (0x3f << 8)
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#define DSPFW_PLANEC_OLD_SHIFT 0
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#define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */
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#define DSPFW_SPRITEA_SHIFT 0
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#define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */
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#define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */
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#define DSPFW3(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
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#define DSPFW_HPLL_SR_EN (1 << 31)
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#define PINEVIEW_SELF_REFRESH_EN (1 << 30)
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#define DSPFW_CURSOR_SR_SHIFT 24
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#define DSPFW_CURSOR_SR_MASK (0x3f << 24)
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#define DSPFW_HPLL_CURSOR_SHIFT 16
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#define DSPFW_HPLL_CURSOR_MASK (0x3f << 16)
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#define DSPFW_HPLL_SR_SHIFT 0
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#define DSPFW_HPLL_SR_MASK (0x1ff << 0)
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/* vlv/chv */
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#define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
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#define DSPFW_SPRITEB_WM1_SHIFT 16
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#define DSPFW_SPRITEB_WM1_MASK (0xff << 16)
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#define DSPFW_CURSORA_WM1_SHIFT 8
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#define DSPFW_CURSORA_WM1_MASK (0x3f << 8)
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#define DSPFW_SPRITEA_WM1_SHIFT 0
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#define DSPFW_SPRITEA_WM1_MASK (0xff << 0)
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#define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
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#define DSPFW_PLANEB_WM1_SHIFT 24
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#define DSPFW_PLANEB_WM1_MASK (0xff << 24)
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#define DSPFW_PLANEA_WM1_SHIFT 16
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#define DSPFW_PLANEA_WM1_MASK (0xff << 16)
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#define DSPFW_CURSORB_WM1_SHIFT 8
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#define DSPFW_CURSORB_WM1_MASK (0x3f << 8)
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#define DSPFW_CURSOR_SR_WM1_SHIFT 0
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#define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0)
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#define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
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#define DSPFW_SR_WM1_SHIFT 0
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#define DSPFW_SR_WM1_MASK (0x1ff << 0)
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#define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)
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#define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
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#define DSPFW_SPRITED_WM1_SHIFT 24
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#define DSPFW_SPRITED_WM1_MASK (0xff << 24)
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#define DSPFW_SPRITED_SHIFT 16
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#define DSPFW_SPRITED_MASK_VLV (0xff << 16)
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#define DSPFW_SPRITEC_WM1_SHIFT 8
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#define DSPFW_SPRITEC_WM1_MASK (0xff << 8)
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#define DSPFW_SPRITEC_SHIFT 0
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#define DSPFW_SPRITEC_MASK_VLV (0xff << 0)
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#define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)
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#define DSPFW_SPRITEF_WM1_SHIFT 24
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#define DSPFW_SPRITEF_WM1_MASK (0xff << 24)
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#define DSPFW_SPRITEF_SHIFT 16
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#define DSPFW_SPRITEF_MASK_VLV (0xff << 16)
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#define DSPFW_SPRITEE_WM1_SHIFT 8
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#define DSPFW_SPRITEE_WM1_MASK (0xff << 8)
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#define DSPFW_SPRITEE_SHIFT 0
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#define DSPFW_SPRITEE_MASK_VLV (0xff << 0)
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#define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
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#define DSPFW_PLANEC_WM1_SHIFT 24
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#define DSPFW_PLANEC_WM1_MASK (0xff << 24)
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#define DSPFW_PLANEC_SHIFT 16
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#define DSPFW_PLANEC_MASK_VLV (0xff << 16)
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#define DSPFW_CURSORC_WM1_SHIFT 8
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#define DSPFW_CURSORC_WM1_MASK (0x3f << 16)
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#define DSPFW_CURSORC_SHIFT 0
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#define DSPFW_CURSORC_MASK (0x3f << 0)
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/* vlv/chv high order bits */
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#define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)
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#define DSPFW_SR_HI_SHIFT 24
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#define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */
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#define DSPFW_SPRITEF_HI_SHIFT 23
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#define DSPFW_SPRITEF_HI_MASK (1 << 23)
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#define DSPFW_SPRITEE_HI_SHIFT 22
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#define DSPFW_SPRITEE_HI_MASK (1 << 22)
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#define DSPFW_PLANEC_HI_SHIFT 21
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#define DSPFW_PLANEC_HI_MASK (1 << 21)
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#define DSPFW_SPRITED_HI_SHIFT 20
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#define DSPFW_SPRITED_HI_MASK (1 << 20)
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#define DSPFW_SPRITEC_HI_SHIFT 16
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#define DSPFW_SPRITEC_HI_MASK (1 << 16)
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#define DSPFW_PLANEB_HI_SHIFT 12
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#define DSPFW_PLANEB_HI_MASK (1 << 12)
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#define DSPFW_SPRITEB_HI_SHIFT 8
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#define DSPFW_SPRITEB_HI_MASK (1 << 8)
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#define DSPFW_SPRITEA_HI_SHIFT 4
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#define DSPFW_SPRITEA_HI_MASK (1 << 4)
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#define DSPFW_PLANEA_HI_SHIFT 0
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#define DSPFW_PLANEA_HI_MASK (1 << 0)
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#define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)
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#define DSPFW_SR_WM1_HI_SHIFT 24
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#define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */
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#define DSPFW_SPRITEF_WM1_HI_SHIFT 23
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#define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23)
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#define DSPFW_SPRITEE_WM1_HI_SHIFT 22
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#define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22)
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#define DSPFW_PLANEC_WM1_HI_SHIFT 21
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#define DSPFW_PLANEC_WM1_HI_MASK (1 << 21)
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#define DSPFW_SPRITED_WM1_HI_SHIFT 20
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#define DSPFW_SPRITED_WM1_HI_MASK (1 << 20)
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#define DSPFW_SPRITEC_WM1_HI_SHIFT 16
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#define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16)
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#define DSPFW_PLANEB_WM1_HI_SHIFT 12
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#define DSPFW_PLANEB_WM1_HI_MASK (1 << 12)
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#define DSPFW_SPRITEB_WM1_HI_SHIFT 8
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#define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8)
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#define DSPFW_SPRITEA_WM1_HI_SHIFT 4
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#define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4)
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#define DSPFW_PLANEA_WM1_HI_SHIFT 0
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#define DSPFW_PLANEA_WM1_HI_MASK (1 << 0)
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/* drain latency register values*/
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#define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
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#define DDL_CURSOR_SHIFT 24
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#define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite))
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#define DDL_PLANE_SHIFT 0
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#define DDL_PRECISION_HIGH (1 << 7)
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#define DDL_PRECISION_LOW (0 << 7)
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#define DRAIN_LATENCY_MASK 0x7f
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/* FIFO watermark sizes etc */
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#define G4X_FIFO_LINE_SIZE 64
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#define I915_FIFO_LINE_SIZE 64
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#define I830_FIFO_LINE_SIZE 32
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#define VALLEYVIEW_FIFO_SIZE 255
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#define G4X_FIFO_SIZE 127
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#define I965_FIFO_SIZE 512
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#define I945_FIFO_SIZE 127
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#define I915_FIFO_SIZE 95
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#define I855GM_FIFO_SIZE 127 /* In cachelines */
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#define I830_FIFO_SIZE 95
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#define VALLEYVIEW_MAX_WM 0xff
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#define G4X_MAX_WM 0x3f
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#define I915_MAX_WM 0x3f
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#define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
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#define PINEVIEW_FIFO_LINE_SIZE 64
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#define PINEVIEW_MAX_WM 0x1ff
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#define PINEVIEW_DFT_WM 0x3f
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#define PINEVIEW_DFT_HPLLOFF_WM 0
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#define PINEVIEW_GUARD_WM 10
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#define PINEVIEW_CURSOR_FIFO 64
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#define PINEVIEW_CURSOR_MAX_WM 0x3f
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#define PINEVIEW_CURSOR_DFT_WM 0
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#define PINEVIEW_CURSOR_GUARD_WM 5
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#define VALLEYVIEW_CURSOR_MAX_WM 64
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#define I965_CURSOR_FIFO 64
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#define I965_CURSOR_MAX_WM 32
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#define I965_CURSOR_DFT_WM 8
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/* define the Watermark register on Ironlake */
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#define _WM0_PIPEA_ILK 0x45100
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#define _WM0_PIPEB_ILK 0x45104
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#define _WM0_PIPEC_IVB 0x45200
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#define WM0_PIPE_ILK(pipe) _MMIO_BASE_PIPE3(0, (pipe), _WM0_PIPEA_ILK, \
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_WM0_PIPEB_ILK, _WM0_PIPEC_IVB)
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#define WM0_PIPE_PRIMARY_MASK REG_GENMASK(31, 16)
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#define WM0_PIPE_SPRITE_MASK REG_GENMASK(15, 8)
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#define WM0_PIPE_CURSOR_MASK REG_GENMASK(7, 0)
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#define WM0_PIPE_PRIMARY(x) REG_FIELD_PREP(WM0_PIPE_PRIMARY_MASK, (x))
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#define WM0_PIPE_SPRITE(x) REG_FIELD_PREP(WM0_PIPE_SPRITE_MASK, (x))
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#define WM0_PIPE_CURSOR(x) REG_FIELD_PREP(WM0_PIPE_CURSOR_MASK, (x))
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#define WM1_LP_ILK _MMIO(0x45108)
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#define WM2_LP_ILK _MMIO(0x4510c)
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#define WM3_LP_ILK _MMIO(0x45110)
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#define WM_LP_ENABLE REG_BIT(31)
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#define WM_LP_LATENCY_MASK REG_GENMASK(30, 24)
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#define WM_LP_FBC_MASK_BDW REG_GENMASK(23, 19)
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#define WM_LP_FBC_MASK_ILK REG_GENMASK(23, 20)
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#define WM_LP_PRIMARY_MASK REG_GENMASK(18, 8)
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#define WM_LP_CURSOR_MASK REG_GENMASK(7, 0)
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#define WM_LP_LATENCY(x) REG_FIELD_PREP(WM_LP_LATENCY_MASK, (x))
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#define WM_LP_FBC_BDW(x) REG_FIELD_PREP(WM_LP_FBC_MASK_BDW, (x))
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#define WM_LP_FBC_ILK(x) REG_FIELD_PREP(WM_LP_FBC_MASK_ILK, (x))
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#define WM_LP_PRIMARY(x) REG_FIELD_PREP(WM_LP_PRIMARY_MASK, (x))
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#define WM_LP_CURSOR(x) REG_FIELD_PREP(WM_LP_CURSOR_MASK, (x))
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#define WM1S_LP_ILK _MMIO(0x45120)
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#define WM2S_LP_IVB _MMIO(0x45124)
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#define WM3S_LP_IVB _MMIO(0x45128)
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#define WM_LP_SPRITE_ENABLE REG_BIT(31) /* ilk/snb WM1S only */
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#define WM_LP_SPRITE_MASK REG_GENMASK(10, 0)
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#define WM_LP_SPRITE(x) REG_FIELD_PREP(WM_LP_SPRITE_MASK, (x))
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#define WM_MISC _MMIO(0x45260)
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#define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
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#define WM_DBG _MMIO(0x45280)
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#define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0)
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#define WM_DBG_DISALLOW_MAXFIFO (1 << 1)
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#define WM_DBG_DISALLOW_SPRITE (1 << 2)
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||
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#endif /* __I9XX_WM_REGS_H__ */
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