linux/drivers/dpll/zl3073x/devlink.h

/* SPDX-License-Identifier: GPL-2.0-only */

#ifndef _ZL3073X_DEVLINK_H
#define _ZL3073X_DEVLINK_H

struct zl3073x_dev;

struct zl3073x_dev *zl3073x_devm_alloc(struct device *dev);

int zl3073x_devlink_register(struct zl3073x_dev *zldev);

#endif /* _ZL3073X_DEVLINK_H */
dpll: Add basic Microchip ZL3073x support Microchip Azurite ZL3073x represents chip family providing DPLL and optionally PHC (PTP) functionality. The chips can be connected be connected over I2C or SPI bus. They have the following characteristics: * up to 5 separate DPLL units (channels) * 5 synthesizers * 10 input pins (references) * 10 outputs * 20 output pins (output pin pair shares one output) * Each reference and output can operate in either differential or single-ended mode (differential mode uses 2 pins) * Each output is connected to one of the synthesizers * Each synthesizer is driven by one of the DPLL unit The device uses 7-bit addresses and 8-bits values. It exposes 8-, 16-, 32- and 48-bits registers in address range <0x000,0x77F>. Due to 7bit addressing, the range is organized into pages of 128 bytes, with each page containing a page selector register at address 0x7F. For reading/writing multi-byte registers, the device supports bulk transfers. Add basic functionality to access device registers, probe functionality both I2C and SPI cases and add devlink support to provide info and to set clock ID parameter. Signed-off-by: Ivan Vecera <ivecera@redhat.com> Reviewed-by: Jiri Pirko <jiri@nvidia.com> Link: https://patch.msgid.link/20250704182202.1641943-6-ivecera@redhat.com Signed-off-by: Jakub Kicinski <kuba@kernel.org> 2025-07-04 20:21:55 +02:00			`/* SPDX-License-Identifier: GPL-2.0-only */`

			`#ifndef _ZL3073X_DEVLINK_H`
			`#define _ZL3073X_DEVLINK_H`

			`struct zl3073x_dev;`

			`struct zl3073x_dev zl3073x_devm_alloc(struct device dev);`

			`int zl3073x_devlink_register(struct zl3073x_dev *zldev);`

			`#endif /* _ZL3073X_DEVLINK_H */`