linux/drivers/dma/amd/Makefile

# SPDX-License-Identifier: GPL-2.0

obj-$(CONFIG_AMD_AE4DMA) += ae4dma/
obj-$(CONFIG_AMD_PTDMA) += ptdma/
obj-$(CONFIG_AMD_QDMA) += qdma/
dmaengine: amd: qdma: Add AMD QDMA driver Adds driver to enable PCIe board which uses AMD QDMA (the Queue-based Direct Memory Access) subsystem. For example, Xilinx Alveo V70 AI Accelerator devices. https://www.xilinx.com/applications/data-center/v70.html The QDMA subsystem is used in conjunction with the PCI Express IP block to provide high performance data transfer between host memory and the card's DMA subsystem. +-------+ +-------+ +-----------+ PCIe \| \| \| \| \| \| Tx/Rx \| \| \| \| AXI \| \| <=======> \| PCIE \| <===> \| QDMA \| <====>\| User Logic\| \| \| \| \| \| \| +-------+ +-------+ +-----------+ The primary mechanism to transfer data using the QDMA is for the QDMA engine to operate on instructions (descriptors) provided by the host operating system. Using the descriptors, the QDMA can move data in both the Host to Card (H2C) direction, or the Card to Host (C2H) direction. The QDMA provides a per-queue basis option whether DMA traffic goes to an AXI4 memory map (MM) interface or to an AXI4-Stream interface. The hardware detail is provided by https://docs.xilinx.com/r/en-US/pg302-qdma Implements dmaengine APIs to support MM DMA transfers. - probe the available DMA channels - use dma_slave_map for channel lookup - use virtual channel to manage dmaengine tx descriptors - implement device_prep_slave_sg callback to handle host scatter gather list Signed-off-by: Nishad Saraf <nishads@amd.com> Signed-off-by: Lizhi Hou <lizhi.hou@amd.com> Link: https://lore.kernel.org/r/20240819211948.688786-2-lizhi.hou@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 2024-08-19 14:19:48 -07:00			`# SPDX-License-Identifier: GPL-2.0`

dmaengine: ae4dma: Add AMD ae4dma controller driver Add support for AMD AE4DMA controller. It performs high-bandwidth memory to memory and IO copy operation. Device commands are managed via a circular queue of 'descriptors', each of which specifies source and destination addresses for copying a single buffer of data. Reviewed-by: Raju Rangoju <Raju.Rangoju@amd.com> Reviewed-by: Philipp Stanner <pstanner@redhat.com> Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com> Link: https://lore.kernel.org/r/20241025095931.726018-3-Basavaraj.Natikar@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 2024-10-25 15:29:27 +05:30			`obj-$(CONFIG_AMD_AE4DMA) += ae4dma/`
dmaengine: Move AMD PTDMA driver to amd directory PTDMA driver is the AMD DMA driver, and newer AMD platforms support newer DMA engines. Hence, move the current drivers to the AMD directory. This would also mean that future driver submissions to the AMD DMA driver will also land in the AMD-specific directory. Reviewed-by: Raju Rangoju <Raju.Rangoju@amd.com> Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com> Link: https://lore.kernel.org/r/20241025095931.726018-2-Basavaraj.Natikar@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 2024-10-25 15:29:26 +05:30			`obj-$(CONFIG_AMD_PTDMA) += ptdma/`
dmaengine: amd: qdma: Add AMD QDMA driver Adds driver to enable PCIe board which uses AMD QDMA (the Queue-based Direct Memory Access) subsystem. For example, Xilinx Alveo V70 AI Accelerator devices. https://www.xilinx.com/applications/data-center/v70.html The QDMA subsystem is used in conjunction with the PCI Express IP block to provide high performance data transfer between host memory and the card's DMA subsystem. +-------+ +-------+ +-----------+ PCIe \| \| \| \| \| \| Tx/Rx \| \| \| \| AXI \| \| <=======> \| PCIE \| <===> \| QDMA \| <====>\| User Logic\| \| \| \| \| \| \| +-------+ +-------+ +-----------+ The primary mechanism to transfer data using the QDMA is for the QDMA engine to operate on instructions (descriptors) provided by the host operating system. Using the descriptors, the QDMA can move data in both the Host to Card (H2C) direction, or the Card to Host (C2H) direction. The QDMA provides a per-queue basis option whether DMA traffic goes to an AXI4 memory map (MM) interface or to an AXI4-Stream interface. The hardware detail is provided by https://docs.xilinx.com/r/en-US/pg302-qdma Implements dmaengine APIs to support MM DMA transfers. - probe the available DMA channels - use dma_slave_map for channel lookup - use virtual channel to manage dmaengine tx descriptors - implement device_prep_slave_sg callback to handle host scatter gather list Signed-off-by: Nishad Saraf <nishads@amd.com> Signed-off-by: Lizhi Hou <lizhi.hou@amd.com> Link: https://lore.kernel.org/r/20240819211948.688786-2-lizhi.hou@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 2024-08-19 14:19:48 -07:00			`obj-$(CONFIG_AMD_QDMA) += qdma/`