linux/arch/riscv/boot/dts/Makefile

# SPDX-License-Identifier: GPL-2.0
subdir-y += allwinner
subdir-y += andes
subdir-y += canaan
subdir-y += microchip
subdir-y += renesas
subdir-y += sifive
subdir-y += sophgo
subdir-y += spacemit
subdir-y += starfive
subdir-y += thead
arch: riscv: add support for building DTB files from DT source data Similar to ARM64, add support for building DTB files from DT source data for RISC-V boards. This patch starts with the infrastructure needed for SiFive boards. Boards from other vendors would add support here in a similar form. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Tested-by: Loys Ollivier <lollivier@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Albert Ou <aou@eecs.berkeley.edu> 2019-05-20 09:19:40 -07:00			`# SPDX-License-Identifier: GPL-2.0`
riscv: dts: allwinner: Add MangoPi MQ devicetree The MangoPi MQ is a tiny SBC built around the Allwinner D1s. Its onboard peripherals include two USB Type-C ports (1 device, 1 host) and RTL8189FTV WLAN. A MangoPi MQ-R variant of the board also exists. The MQ-R has a different form factor, but the onboard peripherals are the same. Most D1 and D1s boards use a similar power tree, with the 1.8V rail powered by the SoC's internal LDOA, analog domains powered by ALDO, and the rest of the board powered by always-on fixed regulators. To avoid duplication, factor out the regulator information that is common across boards. The board also exposes GPIO Port E via a FPC connector, which can support either a camera or an RMII Ethernet PHY. The additional regulators supply that connector. Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Guo Ren <guoren@kernel.org> Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230126045738.47903-6-samuel@sholland.org Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> 2023-01-25 22:57:32 -06:00			`subdir-y += allwinner`
riscv: dts: andes: add Voyager board device tree Introduce the device tree support for Voyager development board. Currently only support booting into console with only uart, other features will be added later. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Link: https://lore.kernel.org/r/20250711133025.2192404-8-ben717@andestech.com Signed-off-by: Arnd Bergmann <arnd@arndb.de> 2025-07-11 21:30:23 +08:00			`subdir-y += andes`
RISC-V: kbuild: convert all use of SOC_FOO to ARCH_FOO Convert all non user visible use of SOC_FOO symbols to their ARCH_FOO variants. The canaan DTs are an outlier in that they're gated at the directory and the file level. Drop the directory level gating while we are swapping the symbol names over. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> 2022-11-20 21:34:44 +00:00			`subdir-y += canaan`
RISC-V: Initial DTS for Microchip ICICLE board Add initial DTS for Microchip ICICLE board having only essential devices (clocks, sdhci, ethernet, serial, etc). The device tree is based on the U-Boot patch. https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.begari@microchip.com/ Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> 2021-03-03 12:02:51 -08:00			`subdir-y += microchip`
riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Enable the minimal blocks required for booting the Renesas RZ/Five SMARC EVK with initramfs. Below are the blocks which are enabled: - CPG - CPU0 - DDR (memory regions) - PINCTRL - PLIC - SCIF0 As we are reusing the RZ/G2UL SoC base DTSI [0], RZ/G2UL SMARC SoM [1] and carrier [2] board DTSIs which enables almost all the blocks supported by the RZ/G2UL SMARC EVK and whereas on RZ/Five SoC we will be gradually enabling the blocks hence the aliases for ETH/I2C are deleted and rest of the IP blocks are marked as disabled/deleted. [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi [1] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi [2] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/20221028165921.94487-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> 2022-10-28 17:59:19 +01:00			`subdir-y += renesas`
riscv: dts: sort makefile entries by directory New additions to the list have tried to respect alphanumeric ordering, but the thing was out of order to start with. Sort it. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> 2023-06-17 21:27:35 +01:00			`subdir-y += sifive`
riscv: dts: sophgo: add Milk-V Pioneer board device tree Milk-V Pioneer [1] is a developer motherboard based on SG2042 in a standard mATX form factor. Currently only support booting into console with only uart enabled, other features will be added soon later. Link: https://milkv.io/pioneer [1] Reviewed-by: Guo Ren <guoren@kernel.org> Acked-by: Chao Wei <chao.wei@sophgo.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> 2023-10-04 23:44:25 +08:00			`subdir-y += sophgo`
riscv: dts: spacemit: add Banana Pi BPI-F3 board device tree Banana Pi BPI-F3 [1] is a industrial grade RISC-V development board, it design with SpacemiT K1 8 core RISC-V chip [2]. Currently only support booting into console with only uart enabled, other features will be added soon later. Link: https://docs.banana-pi.org/en/BPI-F3/BananaPi_BPI-F3 [1] Link: https://www.spacemit.com/en/spacemit-key-stone-2/ [2] Signed-off-by: Yangyu Chen <cyy@cyyself.name> Acked-by: Jesse Taube <jesse@rivosinc.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Yixun Lan <dlan@gentoo.org> 2024-07-30 00:28:12 +00:00			`subdir-y += spacemit`
riscv: dts: sort makefile entries by directory New additions to the list have tried to respect alphanumeric ordering, but the thing was out of order to start with. Sort it. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> 2023-06-17 21:27:35 +01:00			`subdir-y += starfive`
			`subdir-y += thead`