License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 15:07:57 +01:00
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// SPDX-License-Identifier: GPL-2.0
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2005-04-16 15:20:36 -07:00
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/*
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2006-10-03 23:01:26 +02:00
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* linux/arch/m68k/mm/motorola.c
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2005-04-16 15:20:36 -07:00
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*
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* Routines specific to the Motorola MMU, originally from:
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* linux/arch/m68k/init.c
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* which are Copyright (C) 1995 Hamish Macdonald
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*
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* Moved 8/20/1999 Sam Creasey
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*/
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#include <linux/module.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <linux/swap.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/init.h>
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2018-07-04 09:28:16 +03:00
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#include <linux/memblock.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 17:04:11 +09:00
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#include <linux/gfp.h>
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2005-04-16 15:20:36 -07:00
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#include <asm/setup.h>
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2016-12-24 11:46:01 -08:00
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#include <linux/uaccess.h>
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2005-04-16 15:20:36 -07:00
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#include <asm/page.h>
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#include <asm/pgalloc.h>
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#include <asm/machdep.h>
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#include <asm/io.h>
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#ifdef CONFIG_ATARI
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#include <asm/atari_stram.h>
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#endif
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2008-12-21 12:03:37 +01:00
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#include <asm/sections.h>
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2005-04-16 15:20:36 -07:00
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#undef DEBUG
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#ifndef mm_cachebits
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/*
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* Bits to add to page descriptors for "normal" caching mode.
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* For 68020/030 this is 0.
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* For 68040, this is _PAGE_CACHE040 (cachable, copyback)
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*/
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unsigned long mm_cachebits;
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EXPORT_SYMBOL(mm_cachebits);
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#endif
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2020-06-08 21:32:56 -07:00
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/* Prior to calling these routines, the page should have been flushed
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* from both the cache and ATC, or the CPU might not notice that the
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* cache setting for the page has been changed. -jskov
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*/
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static inline void nocache_page(void *vaddr)
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{
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unsigned long addr = (unsigned long)vaddr;
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if (CPU_IS_040_OR_060) {
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2020-06-08 21:33:05 -07:00
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pte_t *ptep = virt_to_kpte(addr);
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2020-06-08 21:32:56 -07:00
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*ptep = pte_mknocache(*ptep);
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}
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}
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static inline void cache_page(void *vaddr)
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{
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unsigned long addr = (unsigned long)vaddr;
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if (CPU_IS_040_OR_060) {
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2020-06-08 21:33:05 -07:00
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pte_t *ptep = virt_to_kpte(addr);
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2020-06-08 21:32:56 -07:00
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*ptep = pte_mkcache(*ptep);
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}
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}
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2020-01-31 13:45:34 +01:00
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/*
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* Motorola 680x0 user's manual recommends using uncached memory for address
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* translation tables.
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*
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* Seeing how the MMU can be external on (some of) these chips, that seems like
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* a very important recommendation to follow. Provide some helpers to combat
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* 'variation' amongst the users of this.
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*/
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void mmu_page_ctor(void *page)
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{
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2023-08-02 16:13:43 +01:00
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__flush_pages_to_ram(page, 1);
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2020-01-31 13:45:34 +01:00
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flush_tlb_kernel_page(page);
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nocache_page(page);
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}
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void mmu_page_dtor(void *page)
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{
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cache_page(page);
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}
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2020-01-31 13:45:35 +01:00
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/* ++andreas: {get,free}_pointer_table rewritten to use unused fields from
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2025-06-10 17:12:55 -07:00
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struct ptdesc instead of separately kmalloced struct. Stolen from
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2020-01-31 13:45:35 +01:00
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arch/sparc/mm/srmmu.c ... */
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typedef struct list_head ptable_desc;
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2020-01-31 13:45:39 +01:00
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2025-01-03 18:44:12 +00:00
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static struct list_head ptable_list[3] = {
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2020-01-31 13:45:39 +01:00
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LIST_HEAD_INIT(ptable_list[0]),
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LIST_HEAD_INIT(ptable_list[1]),
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2025-01-03 18:44:12 +00:00
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LIST_HEAD_INIT(ptable_list[2]),
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2020-01-31 13:45:39 +01:00
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};
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2020-01-31 13:45:35 +01:00
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2025-06-10 17:12:55 -07:00
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#define PD_PTABLE(ptdesc) ((ptable_desc *)&(virt_to_ptdesc((void *)(ptdesc))->pt_list))
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2025-05-16 16:13:29 +01:00
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#define PD_PTDESC(ptable) (list_entry(ptable, struct ptdesc, pt_list))
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#define PD_MARKBITS(dp) (*(unsigned int *)&PD_PTDESC(dp)->pt_index)
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2020-01-31 13:45:39 +01:00
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2025-01-03 18:44:12 +00:00
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static const int ptable_shift[3] = {
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7+2, /* PGD */
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7+2, /* PMD */
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2020-01-31 13:45:39 +01:00
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6+2, /* PTE */
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};
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2020-01-31 13:45:35 +01:00
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2020-01-31 13:45:39 +01:00
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#define ptable_size(type) (1U << ptable_shift[type])
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#define ptable_mask(type) ((1U << (PAGE_SIZE / ptable_size(type))) - 1)
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2020-01-31 13:45:35 +01:00
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2020-01-31 13:45:39 +01:00
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void __init init_pointer_table(void *table, int type)
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2020-01-31 13:45:35 +01:00
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{
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ptable_desc *dp;
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2020-01-31 13:45:39 +01:00
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unsigned long ptable = (unsigned long)table;
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2025-06-10 17:12:54 -07:00
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unsigned long pt_addr = ptable & PAGE_MASK;
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unsigned int mask = 1U << ((ptable - pt_addr)/ptable_size(type));
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2020-01-31 13:45:35 +01:00
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2025-06-10 17:12:54 -07:00
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dp = PD_PTABLE(pt_addr);
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2020-01-31 13:45:35 +01:00
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if (!(PD_MARKBITS(dp) & mask)) {
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2020-01-31 13:45:39 +01:00
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PD_MARKBITS(dp) = ptable_mask(type);
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list_add(dp, &ptable_list[type]);
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2020-01-31 13:45:35 +01:00
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}
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PD_MARKBITS(dp) &= ~mask;
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pr_debug("init_pointer_table: %lx, %x\n", ptable, PD_MARKBITS(dp));
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2025-06-10 17:12:54 -07:00
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/* unreserve the ptdesc so it's possible to free that ptdesc */
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__ClearPageReserved(ptdesc_page(PD_PTDESC(dp)));
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init_page_count(ptdesc_page(PD_PTDESC(dp)));
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2020-01-31 13:45:35 +01:00
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return;
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}
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mm: pass mm down to pagetable_{pte,pmd}_ctor
Patch series "Always call constructor for kernel page tables", v2.
There has been much confusion around exactly when page table
constructors/destructors (pagetable_*_[cd]tor) are supposed to be called.
They were initially introduced for user PTEs only (to support split page
table locks), then at the PMD level for the same purpose. Accounting was
added later on, starting at the PTE level and then moving to higher levels
(PMD, PUD). Finally, with my earlier series "Account page tables at all
levels" [1], the ctor/dtor is run for all levels, all the way to PGD.
I thought this was the end of the story, and it hopefully is for user
pgtables, but I was wrong for what concerns kernel pgtables. The current
situation there makes very little sense:
* At the PTE level, the ctor/dtor is not called (at least in the generic
implementation). Specific helpers are used for kernel pgtables at this
level (pte_{alloc,free}_kernel()) and those have never called the
ctor/dtor, most likely because they were initially irrelevant in the
kernel case.
* At all other levels, the ctor/dtor is normally called. This is
potentially wasteful at the PMD level (more on that later).
This series aims to ensure that the ctor/dtor is always called for kernel
pgtables, as it already is for user pgtables. Besides consistency, the
main motivation is to guarantee that ctor/dtor hooks are systematically
called; this makes it possible to insert hooks to protect page tables [2],
for instance. There is however an extra challenge: split locks are not
used for kernel pgtables, and it would therefore be wasteful to initialise
them (ptlock_init()).
It is worth clarifying exactly when split locks are used. They clearly
are for user pgtables, but as illustrated in commit 61444cde9170 ("ARM:
8591/1: mm: use fully constructed struct pages for EFI pgd allocations"),
they also are for special page tables like efi_mm. The one case where
split locks are definitely unused is pgtables owned by init_mm; this is
consistent with the behaviour of apply_to_pte_range().
The approach chosen in this series is therefore to pass the mm associated
to the pgtables being constructed to pagetable_{pte,pmd}_ctor() (patch 1),
and skip ptlock_init() if mm == &init_mm (patch 3 and 7). This makes it
possible to call the PTE ctor/dtor from pte_{alloc,free}_kernel() without
unintended consequences (patch 3). As a result the accounting functions
are now called at all levels for kernel pgtables, and split locks are
never initialised.
In configurations where ptlocks are dynamically allocated (32-bit,
PREEMPT_RT, etc.) and ARCH_ENABLE_SPLIT_PMD_PTLOCK is selected, this
series results in the removal of a kmem_cache allocation for every kernel
PMD. Additionally, for certain architectures that do not use
<asm-generic/pgalloc.h> such as s390, the same optimisation occurs at the
PTE level.
===
Things get more complicated when it comes to special pgtable allocators
(patch 8-12). All architectures need such allocators to create initial
kernel pgtables; we are not concerned with those as the ctor cannot be
called so early in the boot sequence. However, those allocators may also
be used later in the boot sequence or during normal operations. There are
two main use-cases:
1. Mapping EFI memory: efi_mm (arm, arm64, riscv)
2. arch_add_memory(): init_mm
The ctor is already explicitly run (at the PTE/PMD level) in the first
case, as required for pgtables that are not associated with init_mm.
However the same allocators may also be used for the second use-case (or
others), and this is where it gets messy. Patch 1 calls the ctor with
NULL as mm in those situations, as the actual mm isn't available.
Practically this means that ptlocks will be unconditionally initialised.
This is fine on arm - create_mapping_late() is only used for the EFI
mapping. On arm64, __create_pgd_mapping() is also used by
arch_add_memory(); patch 8/9/11 ensure that ctors are called at all levels
with the appropriate mm. The situation is similar on riscv, but
propagating the mm down to the ctor would require significant refactoring.
Since they are already called unconditionally, this series leaves riscv
no worse off - patch 10 adds comments to clarify the situation.
From a cursory look at other architectures implementing arch_add_memory(),
s390 and x86 may also need a similar treatment to add constructor calls.
This is to be taken care of in a future version or as a follow-up.
===
The complications in those special pgtable allocators beg the question:
does it really make sense to treat efi_mm and init_mm differently in e.g.
apply_to_pte_range()? Maybe what we really need is a way to tell if an mm
corresponds to user memory or not, and never use split locks for non-user
mm's. Feedback and suggestions welcome!
This patch (of 12):
In preparation for calling constructors for all kernel page tables while
eliding unnecessary ptlock initialisation, let's pass down the associated
mm to the PTE/PMD level ctors. (These are the two levels where ptlocks
are used.)
In most cases the mm is already around at the point of calling the ctor so
we simply pass it down. This is however not the case for special page
table allocators:
* arch/arm/mm/mmu.c
* arch/arm64/mm/mmu.c
* arch/riscv/mm/init.c
In those cases, the page tables being allocated are either for standard
kernel memory (init_mm) or special page directories, which may not be
associated to any mm. For now let's pass NULL as mm; this will be refined
where possible in future patches.
No functional change in this patch.
Link: https://lore.kernel.org/linux-mm/20250103184415.2744423-1-kevin.brodsky@arm.com/ [1]
Link: https://lore.kernel.org/linux-hardening/20250203101839.1223008-1-kevin.brodsky@arm.com/ [2]
Link: https://lkml.kernel.org/r/20250408095222.860601-1-kevin.brodsky@arm.com
Link: https://lkml.kernel.org/r/20250408095222.860601-2-kevin.brodsky@arm.com
Signed-off-by: Kevin Brodsky <kevin.brodsky@arm.com>
Reviewed-by: Alexander Gordeev <agordeev@linux.ibm.com> [s390]
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: Andreas Larsson <andreas@gaisler.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: David S. Miller <davem@davemloft.net>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Kevin Brodsky <kevin.brodsky@arm.com>
Cc: Linus Waleij <linus.walleij@linaro.org>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Matthew Wilcox (Oracle) <willy@infradead.org>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Mike Rapoport <rppt@kernel.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Qi Zheng <zhengqi.arch@bytedance.com>
Cc: Ryan Roberts <ryan.roberts@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Yang Shi <yang@os.amperecomputing.com>
Cc: <x86@kernel.org>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2025-04-08 10:52:11 +01:00
|
|
|
void *get_pointer_table(struct mm_struct *mm, int type)
|
2020-01-31 13:45:35 +01:00
|
|
|
{
|
2020-01-31 13:45:39 +01:00
|
|
|
ptable_desc *dp = ptable_list[type].next;
|
|
|
|
|
unsigned int mask = list_empty(&ptable_list[type]) ? 0 : PD_MARKBITS(dp);
|
|
|
|
|
unsigned int tmp, off;
|
2020-01-31 13:45:35 +01:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* For a pointer table for a user process address space, a
|
2025-06-10 17:12:52 -07:00
|
|
|
* table is taken from a ptdesc allocated for the purpose. Each
|
|
|
|
|
* ptdesc can hold 8 pointer tables. The ptdesc is remapped in
|
2020-01-31 13:45:35 +01:00
|
|
|
* virtual address space to be noncacheable.
|
|
|
|
|
*/
|
|
|
|
|
if (mask == 0) {
|
2025-06-10 17:12:52 -07:00
|
|
|
struct ptdesc *ptdesc;
|
2020-01-31 13:45:35 +01:00
|
|
|
ptable_desc *new;
|
2025-06-10 17:12:52 -07:00
|
|
|
void *pt_addr;
|
2020-01-31 13:45:35 +01:00
|
|
|
|
2025-06-10 17:12:52 -07:00
|
|
|
ptdesc = pagetable_alloc(GFP_KERNEL | __GFP_ZERO, 0);
|
|
|
|
|
if (!ptdesc)
|
2020-01-31 13:45:35 +01:00
|
|
|
return NULL;
|
|
|
|
|
|
2025-06-10 17:12:52 -07:00
|
|
|
pt_addr = ptdesc_address(ptdesc);
|
|
|
|
|
|
2025-01-03 18:44:12 +00:00
|
|
|
switch (type) {
|
|
|
|
|
case TABLE_PTE:
|
2020-01-31 13:45:39 +01:00
|
|
|
/*
|
|
|
|
|
* m68k doesn't have SPLIT_PTE_PTLOCKS for not having
|
|
|
|
|
* SMP.
|
|
|
|
|
*/
|
2025-06-10 17:12:52 -07:00
|
|
|
pagetable_pte_ctor(mm, ptdesc);
|
2025-01-03 18:44:12 +00:00
|
|
|
break;
|
|
|
|
|
case TABLE_PMD:
|
2025-06-10 17:12:52 -07:00
|
|
|
pagetable_pmd_ctor(mm, ptdesc);
|
2025-01-03 18:44:12 +00:00
|
|
|
break;
|
2025-01-03 18:44:15 +00:00
|
|
|
case TABLE_PGD:
|
2025-06-10 17:12:52 -07:00
|
|
|
pagetable_pgd_ctor(ptdesc);
|
2025-01-03 18:44:15 +00:00
|
|
|
break;
|
2020-01-31 13:45:39 +01:00
|
|
|
}
|
|
|
|
|
|
2025-06-10 17:12:52 -07:00
|
|
|
mmu_page_ctor(pt_addr);
|
2020-01-31 13:45:35 +01:00
|
|
|
|
2025-06-10 17:12:52 -07:00
|
|
|
new = PD_PTABLE(pt_addr);
|
2020-01-31 13:45:39 +01:00
|
|
|
PD_MARKBITS(new) = ptable_mask(type) - 1;
|
2020-01-31 13:45:35 +01:00
|
|
|
list_add_tail(new, dp);
|
|
|
|
|
|
2025-06-10 17:12:52 -07:00
|
|
|
return (pmd_t *)pt_addr;
|
2020-01-31 13:45:35 +01:00
|
|
|
}
|
|
|
|
|
|
2020-01-31 13:45:39 +01:00
|
|
|
for (tmp = 1, off = 0; (mask & tmp) == 0; tmp <<= 1, off += ptable_size(type))
|
2020-01-31 13:45:35 +01:00
|
|
|
;
|
|
|
|
|
PD_MARKBITS(dp) = mask & ~tmp;
|
|
|
|
|
if (!PD_MARKBITS(dp)) {
|
|
|
|
|
/* move to end of list */
|
2020-01-31 13:45:39 +01:00
|
|
|
list_move_tail(dp, &ptable_list[type]);
|
2020-01-31 13:45:35 +01:00
|
|
|
}
|
2025-06-10 17:12:52 -07:00
|
|
|
return ptdesc_address(PD_PTDESC(dp)) + off;
|
2020-01-31 13:45:35 +01:00
|
|
|
}
|
|
|
|
|
|
2020-01-31 13:45:39 +01:00
|
|
|
int free_pointer_table(void *table, int type)
|
2020-01-31 13:45:35 +01:00
|
|
|
{
|
|
|
|
|
ptable_desc *dp;
|
2020-01-31 13:45:39 +01:00
|
|
|
unsigned long ptable = (unsigned long)table;
|
2025-06-10 17:12:53 -07:00
|
|
|
unsigned long pt_addr = ptable & PAGE_MASK;
|
|
|
|
|
unsigned int mask = 1U << ((ptable - pt_addr)/ptable_size(type));
|
2020-01-31 13:45:35 +01:00
|
|
|
|
2025-06-10 17:12:53 -07:00
|
|
|
dp = PD_PTABLE(pt_addr);
|
2020-01-31 13:45:35 +01:00
|
|
|
if (PD_MARKBITS (dp) & mask)
|
|
|
|
|
panic ("table already free!");
|
|
|
|
|
|
|
|
|
|
PD_MARKBITS (dp) |= mask;
|
|
|
|
|
|
2020-01-31 13:45:39 +01:00
|
|
|
if (PD_MARKBITS(dp) == ptable_mask(type)) {
|
2025-06-10 17:12:53 -07:00
|
|
|
/* all tables in ptdesc are free, free ptdesc */
|
2020-01-31 13:45:35 +01:00
|
|
|
list_del(dp);
|
2025-06-10 17:12:53 -07:00
|
|
|
mmu_page_dtor((void *)pt_addr);
|
|
|
|
|
pagetable_dtor_free(virt_to_ptdesc((void *)pt_addr));
|
2020-01-31 13:45:35 +01:00
|
|
|
return 1;
|
2020-01-31 13:45:39 +01:00
|
|
|
} else if (ptable_list[type].next != dp) {
|
2020-01-31 13:45:35 +01:00
|
|
|
/*
|
|
|
|
|
* move this descriptor to the front of the list, since
|
|
|
|
|
* it has one or more free tables.
|
|
|
|
|
*/
|
2020-01-31 13:45:39 +01:00
|
|
|
list_move(dp, &ptable_list[type]);
|
2020-01-31 13:45:35 +01:00
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2007-05-31 00:40:54 -07:00
|
|
|
/* size of memory already mapped in head.S */
|
2014-04-24 12:24:48 +02:00
|
|
|
extern __initdata unsigned long m68k_init_mapped_size;
|
2007-05-31 00:40:54 -07:00
|
|
|
|
|
|
|
|
extern unsigned long availmem;
|
|
|
|
|
|
2020-01-31 13:45:37 +01:00
|
|
|
static pte_t *last_pte_table __initdata = NULL;
|
|
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
static pte_t * __init kernel_page_table(void)
|
|
|
|
|
{
|
2020-01-31 13:45:37 +01:00
|
|
|
pte_t *pte_table = last_pte_table;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2020-08-26 15:01:03 +02:00
|
|
|
if (PAGE_ALIGNED(last_pte_table)) {
|
2020-08-26 15:04:44 +02:00
|
|
|
pte_table = memblock_alloc_low(PAGE_SIZE, PAGE_SIZE);
|
2020-01-31 13:45:37 +01:00
|
|
|
if (!pte_table) {
|
|
|
|
|
panic("%s: Failed to allocate %lu bytes align=%lx\n",
|
|
|
|
|
__func__, PAGE_SIZE, PAGE_SIZE);
|
|
|
|
|
}
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2020-01-31 13:45:37 +01:00
|
|
|
clear_page(pte_table);
|
|
|
|
|
mmu_page_ctor(pte_table);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2020-01-31 13:45:37 +01:00
|
|
|
last_pte_table = pte_table;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
last_pte_table += PTRS_PER_PTE;
|
|
|
|
|
|
|
|
|
|
return pte_table;
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
|
|
2020-01-31 13:45:37 +01:00
|
|
|
static pmd_t *last_pmd_table __initdata = NULL;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
|
static pmd_t * __init kernel_ptr_table(void)
|
|
|
|
|
{
|
2020-01-31 13:45:37 +01:00
|
|
|
if (!last_pmd_table) {
|
2005-04-16 15:20:36 -07:00
|
|
|
unsigned long pmd, last;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
/* Find the last ptr table that was used in head.S and
|
|
|
|
|
* reuse the remaining space in that page for further
|
|
|
|
|
* ptr tables.
|
|
|
|
|
*/
|
|
|
|
|
last = (unsigned long)kernel_pg_dir;
|
|
|
|
|
for (i = 0; i < PTRS_PER_PGD; i++) {
|
2019-12-04 16:53:59 -08:00
|
|
|
pud_t *pud = (pud_t *)(&kernel_pg_dir[i]);
|
|
|
|
|
|
|
|
|
|
if (!pud_present(*pud))
|
2005-04-16 15:20:36 -07:00
|
|
|
continue;
|
2019-12-04 16:53:59 -08:00
|
|
|
pmd = pgd_page_vaddr(kernel_pg_dir[i]);
|
2005-04-16 15:20:36 -07:00
|
|
|
if (pmd > last)
|
|
|
|
|
last = pmd;
|
|
|
|
|
}
|
|
|
|
|
|
2020-01-31 13:45:37 +01:00
|
|
|
last_pmd_table = (pmd_t *)last;
|
2005-04-16 15:20:36 -07:00
|
|
|
#ifdef DEBUG
|
2020-01-31 13:45:37 +01:00
|
|
|
printk("kernel_ptr_init: %p\n", last_pmd_table);
|
2005-04-16 15:20:36 -07:00
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
2020-01-31 13:45:37 +01:00
|
|
|
last_pmd_table += PTRS_PER_PMD;
|
2020-08-26 15:01:03 +02:00
|
|
|
if (PAGE_ALIGNED(last_pmd_table)) {
|
2020-08-26 15:04:44 +02:00
|
|
|
last_pmd_table = memblock_alloc_low(PAGE_SIZE, PAGE_SIZE);
|
2020-01-31 13:45:37 +01:00
|
|
|
if (!last_pmd_table)
|
2019-03-11 23:30:31 -07:00
|
|
|
panic("%s: Failed to allocate %lu bytes align=%lx\n",
|
|
|
|
|
__func__, PAGE_SIZE, PAGE_SIZE);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
2020-01-31 13:45:37 +01:00
|
|
|
clear_page(last_pmd_table);
|
|
|
|
|
mmu_page_ctor(last_pmd_table);
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
|
|
2020-01-31 13:45:37 +01:00
|
|
|
return last_pmd_table;
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|
|
|
|
|
|
2007-05-31 00:40:54 -07:00
|
|
|
static void __init map_node(int node)
|
2005-04-16 15:20:36 -07:00
|
|
|
{
|
2007-05-31 00:40:54 -07:00
|
|
|
unsigned long physaddr, virtaddr, size;
|
2005-04-16 15:20:36 -07:00
|
|
|
pgd_t *pgd_dir;
|
2019-12-04 16:53:59 -08:00
|
|
|
p4d_t *p4d_dir;
|
|
|
|
|
pud_t *pud_dir;
|
2005-04-16 15:20:36 -07:00
|
|
|
pmd_t *pmd_dir;
|
|
|
|
|
pte_t *pte_dir;
|
|
|
|
|
|
2007-05-31 00:40:54 -07:00
|
|
|
size = m68k_memory[node].size;
|
|
|
|
|
physaddr = m68k_memory[node].addr;
|
|
|
|
|
virtaddr = (unsigned long)phys_to_virt(physaddr);
|
|
|
|
|
physaddr |= m68k_supervisor_cachemode |
|
|
|
|
|
_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY;
|
2005-04-16 15:20:36 -07:00
|
|
|
if (CPU_IS_040_OR_060)
|
|
|
|
|
physaddr |= _PAGE_GLOBAL040;
|
|
|
|
|
|
|
|
|
|
while (size > 0) {
|
|
|
|
|
#ifdef DEBUG
|
m68k: mm: Restructure Motorola MMU page-table layout
The Motorola 68xxx MMUs, 040 (and later) have a fixed 7,7,{5,6}
page-table setup, where the last depends on the page-size selected (8k
vs 4k resp.), and head.S selects 4K pages. For 030 (and earlier) we
explicitly program 7,7,6 and 4K pages in %tc.
However, the current code implements this mightily weird. What it does
is group 16 of those (6 bit) pte tables into one 4k page to not waste
space. The down-side is that that forces pmd_t to be a 16-tuple
pointing to consecutive pte tables.
This breaks the generic code which assumes READ_ONCE(*pmd) will be
word sized.
Therefore implement a straight forward 7,7,6 3 level page-table setup,
with the addition (for 020/030) of (partial) large-page support. For
now this increases the memory footprint for pte-tables 15 fold.
Tested with ARAnyM/68040 emulation.
Suggested-by: Will Deacon <will@kernel.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Will Deacon <will@kernel.org>
Acked-by: Greg Ungerer <gerg@linux-m68k.org>
Tested-by: Michael Schmitz <schmitzmic@gmail.com>
Tested-by: Greg Ungerer <gerg@linux-m68k.org>
Link: https://lore.kernel.org/r/20200131125403.711478295@infradead.org
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2020-01-31 13:45:36 +01:00
|
|
|
if (!(virtaddr & (PMD_SIZE-1)))
|
2005-04-16 15:20:36 -07:00
|
|
|
printk ("\npa=%#lx va=%#lx ", physaddr & PAGE_MASK,
|
|
|
|
|
virtaddr);
|
|
|
|
|
#endif
|
|
|
|
|
pgd_dir = pgd_offset_k(virtaddr);
|
|
|
|
|
if (virtaddr && CPU_IS_020_OR_030) {
|
m68k: mm: Restructure Motorola MMU page-table layout
The Motorola 68xxx MMUs, 040 (and later) have a fixed 7,7,{5,6}
page-table setup, where the last depends on the page-size selected (8k
vs 4k resp.), and head.S selects 4K pages. For 030 (and earlier) we
explicitly program 7,7,6 and 4K pages in %tc.
However, the current code implements this mightily weird. What it does
is group 16 of those (6 bit) pte tables into one 4k page to not waste
space. The down-side is that that forces pmd_t to be a 16-tuple
pointing to consecutive pte tables.
This breaks the generic code which assumes READ_ONCE(*pmd) will be
word sized.
Therefore implement a straight forward 7,7,6 3 level page-table setup,
with the addition (for 020/030) of (partial) large-page support. For
now this increases the memory footprint for pte-tables 15 fold.
Tested with ARAnyM/68040 emulation.
Suggested-by: Will Deacon <will@kernel.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Will Deacon <will@kernel.org>
Acked-by: Greg Ungerer <gerg@linux-m68k.org>
Tested-by: Michael Schmitz <schmitzmic@gmail.com>
Tested-by: Greg Ungerer <gerg@linux-m68k.org>
Link: https://lore.kernel.org/r/20200131125403.711478295@infradead.org
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2020-01-31 13:45:36 +01:00
|
|
|
if (!(virtaddr & (PGDIR_SIZE-1)) &&
|
|
|
|
|
size >= PGDIR_SIZE) {
|
2005-04-16 15:20:36 -07:00
|
|
|
#ifdef DEBUG
|
|
|
|
|
printk ("[very early term]");
|
|
|
|
|
#endif
|
|
|
|
|
pgd_val(*pgd_dir) = physaddr;
|
m68k: mm: Restructure Motorola MMU page-table layout
The Motorola 68xxx MMUs, 040 (and later) have a fixed 7,7,{5,6}
page-table setup, where the last depends on the page-size selected (8k
vs 4k resp.), and head.S selects 4K pages. For 030 (and earlier) we
explicitly program 7,7,6 and 4K pages in %tc.
However, the current code implements this mightily weird. What it does
is group 16 of those (6 bit) pte tables into one 4k page to not waste
space. The down-side is that that forces pmd_t to be a 16-tuple
pointing to consecutive pte tables.
This breaks the generic code which assumes READ_ONCE(*pmd) will be
word sized.
Therefore implement a straight forward 7,7,6 3 level page-table setup,
with the addition (for 020/030) of (partial) large-page support. For
now this increases the memory footprint for pte-tables 15 fold.
Tested with ARAnyM/68040 emulation.
Suggested-by: Will Deacon <will@kernel.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Will Deacon <will@kernel.org>
Acked-by: Greg Ungerer <gerg@linux-m68k.org>
Tested-by: Michael Schmitz <schmitzmic@gmail.com>
Tested-by: Greg Ungerer <gerg@linux-m68k.org>
Link: https://lore.kernel.org/r/20200131125403.711478295@infradead.org
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2020-01-31 13:45:36 +01:00
|
|
|
size -= PGDIR_SIZE;
|
|
|
|
|
virtaddr += PGDIR_SIZE;
|
|
|
|
|
physaddr += PGDIR_SIZE;
|
2005-04-16 15:20:36 -07:00
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
}
|
2019-12-04 16:53:59 -08:00
|
|
|
p4d_dir = p4d_offset(pgd_dir, virtaddr);
|
|
|
|
|
pud_dir = pud_offset(p4d_dir, virtaddr);
|
|
|
|
|
if (!pud_present(*pud_dir)) {
|
2005-04-16 15:20:36 -07:00
|
|
|
pmd_dir = kernel_ptr_table();
|
|
|
|
|
#ifdef DEBUG
|
|
|
|
|
printk ("[new pointer %p]", pmd_dir);
|
|
|
|
|
#endif
|
2019-12-04 16:53:59 -08:00
|
|
|
pud_set(pud_dir, pmd_dir);
|
2005-04-16 15:20:36 -07:00
|
|
|
} else
|
2019-12-04 16:53:59 -08:00
|
|
|
pmd_dir = pmd_offset(pud_dir, virtaddr);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
|
if (CPU_IS_020_OR_030) {
|
|
|
|
|
if (virtaddr) {
|
|
|
|
|
#ifdef DEBUG
|
|
|
|
|
printk ("[early term]");
|
|
|
|
|
#endif
|
m68k: mm: Restructure Motorola MMU page-table layout
The Motorola 68xxx MMUs, 040 (and later) have a fixed 7,7,{5,6}
page-table setup, where the last depends on the page-size selected (8k
vs 4k resp.), and head.S selects 4K pages. For 030 (and earlier) we
explicitly program 7,7,6 and 4K pages in %tc.
However, the current code implements this mightily weird. What it does
is group 16 of those (6 bit) pte tables into one 4k page to not waste
space. The down-side is that that forces pmd_t to be a 16-tuple
pointing to consecutive pte tables.
This breaks the generic code which assumes READ_ONCE(*pmd) will be
word sized.
Therefore implement a straight forward 7,7,6 3 level page-table setup,
with the addition (for 020/030) of (partial) large-page support. For
now this increases the memory footprint for pte-tables 15 fold.
Tested with ARAnyM/68040 emulation.
Suggested-by: Will Deacon <will@kernel.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Will Deacon <will@kernel.org>
Acked-by: Greg Ungerer <gerg@linux-m68k.org>
Tested-by: Michael Schmitz <schmitzmic@gmail.com>
Tested-by: Greg Ungerer <gerg@linux-m68k.org>
Link: https://lore.kernel.org/r/20200131125403.711478295@infradead.org
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2020-01-31 13:45:36 +01:00
|
|
|
pmd_val(*pmd_dir) = physaddr;
|
|
|
|
|
physaddr += PMD_SIZE;
|
2005-04-16 15:20:36 -07:00
|
|
|
} else {
|
|
|
|
|
int i;
|
|
|
|
|
#ifdef DEBUG
|
|
|
|
|
printk ("[zero map]");
|
|
|
|
|
#endif
|
2020-01-31 13:45:37 +01:00
|
|
|
pte_dir = kernel_page_table();
|
m68k: mm: Restructure Motorola MMU page-table layout
The Motorola 68xxx MMUs, 040 (and later) have a fixed 7,7,{5,6}
page-table setup, where the last depends on the page-size selected (8k
vs 4k resp.), and head.S selects 4K pages. For 030 (and earlier) we
explicitly program 7,7,6 and 4K pages in %tc.
However, the current code implements this mightily weird. What it does
is group 16 of those (6 bit) pte tables into one 4k page to not waste
space. The down-side is that that forces pmd_t to be a 16-tuple
pointing to consecutive pte tables.
This breaks the generic code which assumes READ_ONCE(*pmd) will be
word sized.
Therefore implement a straight forward 7,7,6 3 level page-table setup,
with the addition (for 020/030) of (partial) large-page support. For
now this increases the memory footprint for pte-tables 15 fold.
Tested with ARAnyM/68040 emulation.
Suggested-by: Will Deacon <will@kernel.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Will Deacon <will@kernel.org>
Acked-by: Greg Ungerer <gerg@linux-m68k.org>
Tested-by: Michael Schmitz <schmitzmic@gmail.com>
Tested-by: Greg Ungerer <gerg@linux-m68k.org>
Link: https://lore.kernel.org/r/20200131125403.711478295@infradead.org
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2020-01-31 13:45:36 +01:00
|
|
|
pmd_set(pmd_dir, pte_dir);
|
|
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
pte_val(*pte_dir++) = 0;
|
|
|
|
|
physaddr += PAGE_SIZE;
|
m68k: mm: Restructure Motorola MMU page-table layout
The Motorola 68xxx MMUs, 040 (and later) have a fixed 7,7,{5,6}
page-table setup, where the last depends on the page-size selected (8k
vs 4k resp.), and head.S selects 4K pages. For 030 (and earlier) we
explicitly program 7,7,6 and 4K pages in %tc.
However, the current code implements this mightily weird. What it does
is group 16 of those (6 bit) pte tables into one 4k page to not waste
space. The down-side is that that forces pmd_t to be a 16-tuple
pointing to consecutive pte tables.
This breaks the generic code which assumes READ_ONCE(*pmd) will be
word sized.
Therefore implement a straight forward 7,7,6 3 level page-table setup,
with the addition (for 020/030) of (partial) large-page support. For
now this increases the memory footprint for pte-tables 15 fold.
Tested with ARAnyM/68040 emulation.
Suggested-by: Will Deacon <will@kernel.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Will Deacon <will@kernel.org>
Acked-by: Greg Ungerer <gerg@linux-m68k.org>
Tested-by: Michael Schmitz <schmitzmic@gmail.com>
Tested-by: Greg Ungerer <gerg@linux-m68k.org>
Link: https://lore.kernel.org/r/20200131125403.711478295@infradead.org
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2020-01-31 13:45:36 +01:00
|
|
|
for (i = 1; i < PTRS_PER_PTE; physaddr += PAGE_SIZE, i++)
|
2005-04-16 15:20:36 -07:00
|
|
|
pte_val(*pte_dir++) = physaddr;
|
|
|
|
|
}
|
m68k: mm: Restructure Motorola MMU page-table layout
The Motorola 68xxx MMUs, 040 (and later) have a fixed 7,7,{5,6}
page-table setup, where the last depends on the page-size selected (8k
vs 4k resp.), and head.S selects 4K pages. For 030 (and earlier) we
explicitly program 7,7,6 and 4K pages in %tc.
However, the current code implements this mightily weird. What it does
is group 16 of those (6 bit) pte tables into one 4k page to not waste
space. The down-side is that that forces pmd_t to be a 16-tuple
pointing to consecutive pte tables.
This breaks the generic code which assumes READ_ONCE(*pmd) will be
word sized.
Therefore implement a straight forward 7,7,6 3 level page-table setup,
with the addition (for 020/030) of (partial) large-page support. For
now this increases the memory footprint for pte-tables 15 fold.
Tested with ARAnyM/68040 emulation.
Suggested-by: Will Deacon <will@kernel.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Will Deacon <will@kernel.org>
Acked-by: Greg Ungerer <gerg@linux-m68k.org>
Tested-by: Michael Schmitz <schmitzmic@gmail.com>
Tested-by: Greg Ungerer <gerg@linux-m68k.org>
Link: https://lore.kernel.org/r/20200131125403.711478295@infradead.org
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2020-01-31 13:45:36 +01:00
|
|
|
size -= PMD_SIZE;
|
|
|
|
|
virtaddr += PMD_SIZE;
|
2005-04-16 15:20:36 -07:00
|
|
|
} else {
|
|
|
|
|
if (!pmd_present(*pmd_dir)) {
|
|
|
|
|
#ifdef DEBUG
|
|
|
|
|
printk ("[new table]");
|
|
|
|
|
#endif
|
|
|
|
|
pte_dir = kernel_page_table();
|
|
|
|
|
pmd_set(pmd_dir, pte_dir);
|
|
|
|
|
}
|
|
|
|
|
pte_dir = pte_offset_kernel(pmd_dir, virtaddr);
|
|
|
|
|
|
|
|
|
|
if (virtaddr) {
|
|
|
|
|
if (!pte_present(*pte_dir))
|
|
|
|
|
pte_val(*pte_dir) = physaddr;
|
|
|
|
|
} else
|
|
|
|
|
pte_val(*pte_dir) = 0;
|
|
|
|
|
size -= PAGE_SIZE;
|
|
|
|
|
virtaddr += PAGE_SIZE;
|
|
|
|
|
physaddr += PAGE_SIZE;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
#ifdef DEBUG
|
|
|
|
|
printk("\n");
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
2022-07-11 12:35:55 +05:30
|
|
|
/*
|
|
|
|
|
* Alternate definitions that are compile time constants, for
|
|
|
|
|
* initializing protection_map. The cachebits are fixed later.
|
|
|
|
|
*/
|
|
|
|
|
#define PAGE_NONE_C __pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED)
|
|
|
|
|
#define PAGE_SHARED_C __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
|
|
|
|
|
#define PAGE_COPY_C __pgprot(_PAGE_PRESENT | _PAGE_RONLY | _PAGE_ACCESSED)
|
|
|
|
|
#define PAGE_READONLY_C __pgprot(_PAGE_PRESENT | _PAGE_RONLY | _PAGE_ACCESSED)
|
|
|
|
|
|
|
|
|
|
static pgprot_t protection_map[16] __ro_after_init = {
|
|
|
|
|
[VM_NONE] = PAGE_NONE_C,
|
|
|
|
|
[VM_READ] = PAGE_READONLY_C,
|
|
|
|
|
[VM_WRITE] = PAGE_COPY_C,
|
|
|
|
|
[VM_WRITE | VM_READ] = PAGE_COPY_C,
|
|
|
|
|
[VM_EXEC] = PAGE_READONLY_C,
|
|
|
|
|
[VM_EXEC | VM_READ] = PAGE_READONLY_C,
|
|
|
|
|
[VM_EXEC | VM_WRITE] = PAGE_COPY_C,
|
|
|
|
|
[VM_EXEC | VM_WRITE | VM_READ] = PAGE_COPY_C,
|
|
|
|
|
[VM_SHARED] = PAGE_NONE_C,
|
|
|
|
|
[VM_SHARED | VM_READ] = PAGE_READONLY_C,
|
|
|
|
|
[VM_SHARED | VM_WRITE] = PAGE_SHARED_C,
|
|
|
|
|
[VM_SHARED | VM_WRITE | VM_READ] = PAGE_SHARED_C,
|
|
|
|
|
[VM_SHARED | VM_EXEC] = PAGE_READONLY_C,
|
|
|
|
|
[VM_SHARED | VM_EXEC | VM_READ] = PAGE_READONLY_C,
|
|
|
|
|
[VM_SHARED | VM_EXEC | VM_WRITE] = PAGE_SHARED_C,
|
|
|
|
|
[VM_SHARED | VM_EXEC | VM_WRITE | VM_READ] = PAGE_SHARED_C
|
|
|
|
|
};
|
|
|
|
|
DECLARE_VM_GET_PAGE_PROT
|
|
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
/*
|
|
|
|
|
* paging_init() continues the virtual memory environment setup which
|
|
|
|
|
* was begun by the code in arch/head.S.
|
|
|
|
|
*/
|
|
|
|
|
void __init paging_init(void)
|
|
|
|
|
{
|
2020-06-03 15:57:32 -07:00
|
|
|
unsigned long max_zone_pfn[MAX_NR_ZONES] = { 0, };
|
2007-05-31 00:40:54 -07:00
|
|
|
unsigned long min_addr, max_addr;
|
2018-07-04 09:28:16 +03:00
|
|
|
unsigned long addr;
|
2007-05-31 00:40:54 -07:00
|
|
|
int i;
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
|
#ifdef DEBUG
|
2007-08-22 14:01:30 -07:00
|
|
|
printk ("start of paging_init (%p, %lx)\n", kernel_pg_dir, availmem);
|
2005-04-16 15:20:36 -07:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* Fix the cache mode in the page descriptors for the 680[46]0. */
|
|
|
|
|
if (CPU_IS_040_OR_060) {
|
|
|
|
|
int i;
|
|
|
|
|
#ifndef mm_cachebits
|
|
|
|
|
mm_cachebits = _PAGE_CACHE040;
|
|
|
|
|
#endif
|
|
|
|
|
for (i = 0; i < 16; i++)
|
|
|
|
|
pgprot_val(protection_map[i]) |= _PAGE_CACHE040;
|
|
|
|
|
}
|
|
|
|
|
|
2007-05-31 00:40:54 -07:00
|
|
|
min_addr = m68k_memory[0].addr;
|
2023-02-23 12:23:49 +01:00
|
|
|
max_addr = min_addr + m68k_memory[0].size - 1;
|
2021-11-05 13:44:49 -07:00
|
|
|
memblock_add_node(m68k_memory[0].addr, m68k_memory[0].size, 0,
|
|
|
|
|
MEMBLOCK_NONE);
|
2007-05-31 00:40:54 -07:00
|
|
|
for (i = 1; i < m68k_num_memory;) {
|
|
|
|
|
if (m68k_memory[i].addr < min_addr) {
|
|
|
|
|
printk("Ignoring memory chunk at 0x%lx:0x%lx before the first chunk\n",
|
|
|
|
|
m68k_memory[i].addr, m68k_memory[i].size);
|
|
|
|
|
printk("Fix your bootloader or use a memfile to make use of this area!\n");
|
|
|
|
|
m68k_num_memory--;
|
|
|
|
|
memmove(m68k_memory + i, m68k_memory + i + 1,
|
2013-10-02 21:50:56 +02:00
|
|
|
(m68k_num_memory - i) * sizeof(struct m68k_mem_info));
|
2007-05-31 00:40:54 -07:00
|
|
|
continue;
|
|
|
|
|
}
|
2021-11-05 13:44:49 -07:00
|
|
|
memblock_add_node(m68k_memory[i].addr, m68k_memory[i].size, i,
|
|
|
|
|
MEMBLOCK_NONE);
|
2023-02-23 12:23:49 +01:00
|
|
|
addr = m68k_memory[i].addr + m68k_memory[i].size - 1;
|
2007-05-31 00:40:54 -07:00
|
|
|
if (addr > max_addr)
|
|
|
|
|
max_addr = addr;
|
|
|
|
|
i++;
|
|
|
|
|
}
|
|
|
|
|
m68k_memoffset = min_addr - PAGE_OFFSET;
|
2023-02-23 12:23:49 +01:00
|
|
|
m68k_virt_to_node_shift = fls(max_addr - min_addr) - 6;
|
2007-05-31 00:40:54 -07:00
|
|
|
|
2007-05-31 00:40:50 -07:00
|
|
|
module_fixup(NULL, __start_fixup, __stop_fixup);
|
|
|
|
|
flush_icache();
|
|
|
|
|
|
2023-02-23 12:23:49 +01:00
|
|
|
high_memory = phys_to_virt(max_addr) + 1;
|
2007-05-31 00:40:54 -07:00
|
|
|
|
|
|
|
|
min_low_pfn = availmem >> PAGE_SHIFT;
|
2023-02-23 12:23:49 +01:00
|
|
|
max_pfn = max_low_pfn = (max_addr >> PAGE_SHIFT) + 1;
|
2007-05-31 00:40:54 -07:00
|
|
|
|
2018-07-04 09:28:16 +03:00
|
|
|
/* Reserve kernel text/data/bss and the memory allocated in head.S */
|
|
|
|
|
memblock_reserve(m68k_memory[0].addr, availmem - m68k_memory[0].addr);
|
2007-05-31 00:40:54 -07:00
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
/*
|
|
|
|
|
* Map the physical memory available into the kernel virtual
|
2018-07-04 09:28:16 +03:00
|
|
|
* address space. Make sure memblock will not try to allocate
|
|
|
|
|
* pages beyond the memory we already mapped in head.S
|
2005-04-16 15:20:36 -07:00
|
|
|
*/
|
2018-07-04 09:28:16 +03:00
|
|
|
memblock_set_bottom_up(true);
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < m68k_num_memory; i++) {
|
|
|
|
|
m68k_setup_node(i);
|
2007-05-31 00:40:54 -07:00
|
|
|
map_node(i);
|
2018-07-04 09:28:16 +03:00
|
|
|
}
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
|
flush_tlb_all();
|
|
|
|
|
|
2021-11-19 09:29:38 +11:00
|
|
|
early_memtest(min_addr, max_addr);
|
|
|
|
|
|
2005-04-16 15:20:36 -07:00
|
|
|
/*
|
|
|
|
|
* initialize the bad page table and bad page to point
|
|
|
|
|
* to a couple of allocated pages
|
|
|
|
|
*/
|
2025-01-02 15:25:28 +08:00
|
|
|
empty_zero_page = memblock_alloc_or_panic(PAGE_SIZE, PAGE_SIZE);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Set up SFC/DFC registers
|
|
|
|
|
*/
|
2021-09-16 09:04:05 +02:00
|
|
|
set_fc(USER_DATA);
|
2005-04-16 15:20:36 -07:00
|
|
|
|
|
|
|
|
#ifdef DEBUG
|
|
|
|
|
printk ("before free_area_init\n");
|
|
|
|
|
#endif
|
2020-06-03 15:57:32 -07:00
|
|
|
for (i = 0; i < m68k_num_memory; i++)
|
2011-04-26 14:51:53 +12:00
|
|
|
if (node_present_pages(i))
|
|
|
|
|
node_set_state(i, N_NORMAL_MEMORY);
|
2020-06-03 15:57:32 -07:00
|
|
|
|
|
|
|
|
max_zone_pfn[ZONE_DMA] = memblock_end_of_DRAM();
|
|
|
|
|
free_area_init(max_zone_pfn);
|
2005-04-16 15:20:36 -07:00
|
|
|
}
|