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53 lines
1.4 KiB
C
53 lines
1.4 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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#include <kvm/arm_vgic.h>
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#include <linux/irqchip/arm-vgic-info.h>
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#include "vgic.h"
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/*
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* Probe for a vGICv5 compatible interrupt controller, returning 0 on success.
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* Currently only supports GICv3-based VMs on a GICv5 host, and hence only
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* registers a VGIC_V3 device.
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*/
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int vgic_v5_probe(const struct gic_kvm_info *info)
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{
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u64 ich_vtr_el2;
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int ret;
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if (!info->has_gcie_v3_compat)
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return -ENODEV;
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kvm_vgic_global_state.type = VGIC_V5;
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kvm_vgic_global_state.has_gcie_v3_compat = true;
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/* We only support v3 compat mode - use vGICv3 limits */
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kvm_vgic_global_state.max_gic_vcpus = VGIC_V3_MAX_CPUS;
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kvm_vgic_global_state.vcpu_base = 0;
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kvm_vgic_global_state.vctrl_base = NULL;
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kvm_vgic_global_state.can_emulate_gicv2 = false;
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kvm_vgic_global_state.has_gicv4 = false;
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kvm_vgic_global_state.has_gicv4_1 = false;
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ich_vtr_el2 = kvm_call_hyp_ret(__vgic_v3_get_gic_config);
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kvm_vgic_global_state.ich_vtr_el2 = (u32)ich_vtr_el2;
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/*
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* The ListRegs field is 5 bits, but there is an architectural
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* maximum of 16 list registers. Just ignore bit 4...
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*/
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kvm_vgic_global_state.nr_lr = (ich_vtr_el2 & 0xf) + 1;
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ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V3);
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if (ret) {
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kvm_err("Cannot register GICv3-legacy KVM device.\n");
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return ret;
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}
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static_branch_enable(&kvm_vgic_global_state.gicv3_cpuif);
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kvm_info("GCIE legacy system register CPU interface\n");
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return 0;
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}
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