2017-12-15 12:44:26 +01:00
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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2016-04-27 15:54:53 +08:00
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/*
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* Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
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*/
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/dts-v1/;
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#include <dt-bindings/pwm/pwm.h>
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arm64: dts: rockchip: Move RK3399 OPPs to dtsi files for SoC variants
Rename the Rockchip RK3399 SoC dtsi files and, consequently, adjust their
contents and the contents of the affected board dts(i) files appropriately,
to "encapsulate" the different CPU and GPU OPPs for each of the supported
RK3399 SoC variants into the respective SoC variant dtsi files.
Moving the OPPs to the SoC variant dtsi files, instead of requiring the
board dts(i) files to include both the SoC variant dtsi file and the right
OPP variant dtsi file, reduces the possibility for mismatched inclusion and
improves the overall hierarchical representation of data.
These changes follow the approach used for the Rockchip RK3588 SoC variants,
which was introduced and described further in commit def88eb4d836 ("arm64:
dts: rockchip: Prepare RK3588 SoC dtsi files for per-variant OPPs"). Please
see that commit for a more detailed explanation.
No functional changes are introduced, which was validated by decompiling and
comparing all affected dtb files before and after these changes. In more
detail, all decompiled dtb files remain exactly the same, except the files
list below, which results from all of them stemming from the same base board
dtsi file (rk3399-rock-pi-4.dtsi), while all of them include one of the three
different RK3399 SoC variant dtsi files by themselves:
- rk3399-rock-4se.dtb
- rk3399-rock-pi-4a.dtb
- rk3399-rock-pi-4a-plus.dtb
- rk3399-rock-pi-4b.dtb
- rk3399-rock-pi-4b-plus.dtb
- rk3399-rock-pi-4c.dtb
When compared with the decompiled original dtb files, these dtb files have
some of their blocks shuffled around a bit and some of their phandles have
different values, as a result of the changes to the order in which the
building blocks from the parent dtsi files are included into them, but they
still effectively remain the same as the originals.
The only exception to the "include only a SoC variant dtsi" is found in
rk3399-evb.dts, which includes rk3399-base.dtsi instead of rk3399.dtsi.
This is intentional, because this board dts file doesn't enable the TSADC,
so including rk3399.dtsi would enable the SoC to go into higher OPPs with
no thermal throttling in place. Let's hope that people interested in this
board will fix this in the future.
As a side note, due to the nature of introduced changes, this commit is best
viewed using the --break-rewrites option for git-log(1).
Related-to: def88eb4d836 ("arm64: dts: rockchip: Prepare RK3588 SoC dtsi files for per-variant OPPs")
Signed-off-by: Dragan Simic <dsimic@manjaro.org>
Link: https://lore.kernel.org/r/9417b5c5b64f9aceea64530a85a536169a3e7466.1721532747.git.dsimic@manjaro.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-07-21 05:45:16 +02:00
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#include "rk3399-base.dtsi"
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2016-04-27 15:54:53 +08:00
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/ {
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model = "Rockchip RK3399 Evaluation Board";
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arm64: dts: rockchip: fix compatible property for rk3399-evb
A test with the command below gives this error:
arch/arm64/boot/dts/rockchip/rk3399-evb.dt.yaml: /: compatible:
['rockchip,rk3399-evb', 'rockchip,rk3399', 'google,rk3399evb-rev2']
is not valid under any of the given schemas
'google,rk3399evb-rev2' was a no longer used variant for Google.
The binding only mentions 'rockchip,rk3399-evb', 'rockchip,rk3399',
so fix this error by removing 'google,rk3399evb-rev2' from
the compatible property in rk3399-evb.dts and change it into
generic rk3399-evb support only.
make ARCH=arm64 dtbs_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/arm/rockchip.yaml
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20200302092759.3291-3-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-03-02 10:27:59 +01:00
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compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
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2016-04-27 15:54:53 +08:00
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2021-03-24 13:22:35 +01:00
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aliases {
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2023-12-12 08:53:48 +01:00
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ethernet0 = &gmac;
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2021-03-24 13:22:35 +01:00
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mmc0 = &sdhci;
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};
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2016-11-09 21:21:57 +08:00
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backlight: backlight {
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compatible = "pwm-backlight";
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brightness-levels = <
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0 1 2 3 4 5 6 7
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8 9 10 11 12 13 14 15
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16 17 18 19 20 21 22 23
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24 25 26 27 28 29 30 31
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32 33 34 35 36 37 38 39
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40 41 42 43 44 45 46 47
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48 49 50 51 52 53 54 55
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56 57 58 59 60 61 62 63
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64 65 66 67 68 69 70 71
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72 73 74 75 76 77 78 79
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80 81 82 83 84 85 86 87
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88 89 90 91 92 93 94 95
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96 97 98 99 100 101 102 103
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104 105 106 107 108 109 110 111
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112 113 114 115 116 117 118 119
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120 121 122 123 124 125 126 127
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128 129 130 131 132 133 134 135
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136 137 138 139 140 141 142 143
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144 145 146 147 148 149 150 151
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152 153 154 155 156 157 158 159
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160 161 162 163 164 165 166 167
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168 169 170 171 172 173 174 175
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176 177 178 179 180 181 182 183
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184 185 186 187 188 189 190 191
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192 193 194 195 196 197 198 199
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200 201 202 203 204 205 206 207
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208 209 210 211 212 213 214 215
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216 217 218 219 220 221 222 223
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224 225 226 227 228 229 230 231
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232 233 234 235 236 237 238 239
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240 241 242 243 244 245 246 247
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248 249 250 251 252 253 254 255>;
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default-brightness-level = <200>;
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pwms = <&pwm0 0 25000 0>;
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};
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2020-03-05 19:39:12 +08:00
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edp_panel: edp-panel {
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2022-05-26 22:42:16 +02:00
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compatible = "lg,lp079qx1-sp0v";
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2020-03-05 19:39:12 +08:00
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backlight = <&backlight>;
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enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
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power-supply = <&vcc3v3_s0>;
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port {
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panel_in_edp: endpoint {
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remote-endpoint = <&edp_out_panel>;
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};
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};
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};
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2016-09-02 01:50:04 +08:00
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clkin_gmac: external-gmac-clock {
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compatible = "fixed-clock";
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clock-frequency = <125000000>;
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clock-output-names = "clkin_gmac";
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#clock-cells = <0>;
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};
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2024-10-05 22:40:12 +02:00
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vdd_center: regulator-vdd-center {
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2016-04-27 15:54:53 +08:00
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compatible = "pwm-regulator";
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pwms = <&pwm3 0 25000 0>;
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regulator-name = "vdd_center";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1400000>;
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regulator-always-on;
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regulator-boot-on;
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status = "okay";
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};
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2024-10-05 22:40:12 +02:00
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vcc3v3_sys: regulator-vcc3v3-sys {
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2016-04-27 15:54:53 +08:00
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_sys";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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2024-10-05 22:40:12 +02:00
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vcc5v0_sys: regulator-vcc5v0-sys {
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2016-07-22 15:00:46 +08:00
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_sys";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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2024-10-05 22:40:12 +02:00
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vcc5v0_host: regulator-vcc5v0-host {
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2016-07-22 15:00:46 +08:00
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compatible = "regulator-fixed";
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enable-active-high;
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2016-10-22 20:59:04 +08:00
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gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
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2016-07-22 15:00:46 +08:00
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pinctrl-names = "default";
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pinctrl-0 = <&vcc5v0_host_en>;
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regulator-name = "vcc5v0_host";
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vin-supply = <&vcc5v0_sys>;
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};
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2024-10-05 22:40:12 +02:00
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vcc_phy: regulator-vcc-phy {
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2016-04-27 15:54:53 +08:00
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compatible = "regulator-fixed";
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regulator-name = "vcc_phy";
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regulator-always-on;
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regulator-boot-on;
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};
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2016-09-02 01:50:04 +08:00
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2024-10-05 22:40:12 +02:00
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vcc_phy: regulator-vcc-phy {
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2016-09-02 01:50:04 +08:00
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compatible = "regulator-fixed";
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regulator-name = "vcc_phy";
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regulator-always-on;
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regulator-boot-on;
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};
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2016-04-27 15:54:53 +08:00
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};
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2020-03-05 19:39:12 +08:00
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&edp {
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status = "okay";
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force-hpd;
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ports {
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edp_out: port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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edp_out_panel: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&panel_in_edp>;
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};
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};
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};
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};
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2016-05-13 15:12:04 -07:00
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&emmc_phy {
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status = "okay";
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};
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2016-09-02 01:50:04 +08:00
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&gmac {
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assigned-clocks = <&cru SCLK_RMII_SRC>;
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assigned-clock-parents = <&clkin_gmac>;
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clock_in_out = "input";
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phy-supply = <&vcc_phy>;
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phy-mode = "rgmii";
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii_pins>;
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2016-10-22 20:59:04 +08:00
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snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
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2016-09-02 01:50:04 +08:00
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snps,reset-active-low;
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snps,reset-delays-us = <0 10000 50000>;
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tx_delay = <0x28>;
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rx_delay = <0x11>;
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status = "okay";
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};
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2020-03-05 19:39:10 +08:00
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&i2c0 {
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status = "okay";
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rk808: pmic@1b {
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compatible = "rockchip,rk808";
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reg = <0x1b>;
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interrupt-parent = <&gpio1>;
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interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&pmic_int_l>;
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2024-10-08 12:48:04 +02:00
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system-power-controller;
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2020-03-05 19:39:10 +08:00
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wakeup-source;
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#clock-cells = <1>;
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clock-output-names = "rk808-clkout1", "rk808-clkout2";
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vcc1-supply = <&vcc3v3_sys>;
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vcc2-supply = <&vcc3v3_sys>;
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vcc3-supply = <&vcc3v3_sys>;
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vcc4-supply = <&vcc3v3_sys>;
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vcc6-supply = <&vcc3v3_sys>;
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vcc7-supply = <&vcc3v3_sys>;
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vcc8-supply = <&vcc3v3_sys>;
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vcc9-supply = <&vcc3v3_sys>;
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vcc10-supply = <&vcc3v3_sys>;
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vcc11-supply = <&vcc3v3_sys>;
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vcc12-supply = <&vcc3v3_sys>;
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vddio-supply = <&vcc1v8_pmu>;
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regulators {
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vdd_log: DCDC_REG1 {
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regulator-name = "vdd_log";
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regulator-min-microvolt = <750000>;
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regulator-max-microvolt = <1350000>;
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regulator-ramp-delay = <6001>;
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regulator-always-on;
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regulator-boot-on;
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regulator-state-mem {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <900000>;
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};
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};
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vdd_cpu_l: DCDC_REG2 {
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regulator-name = "vdd_cpu_l";
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regulator-min-microvolt = <750000>;
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regulator-max-microvolt = <1350000>;
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regulator-ramp-delay = <6001>;
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regulator-always-on;
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regulator-boot-on;
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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vcc_ddr: DCDC_REG3 {
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regulator-name = "vcc_ddr";
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regulator-always-on;
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regulator-boot-on;
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regulator-state-mem {
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regulator-on-in-suspend;
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};
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};
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vcc_1v8: DCDC_REG4 {
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regulator-name = "vcc_1v8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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regulator-state-mem {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <1800000>;
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};
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};
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vcc1v8_dvp: LDO_REG1 {
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regulator-name = "vcc1v8_dvp";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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vcc3v0_tp: LDO_REG2 {
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regulator-name = "vcc3v0_tp";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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regulator-always-on;
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regulator-boot-on;
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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vcc1v8_pmu: LDO_REG3 {
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regulator-name = "vcc1v8_pmu";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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regulator-state-mem {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <1800000>;
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};
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};
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vcc_sd: LDO_REG4 {
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regulator-name = "vcc_sd";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3000000>;
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regulator-always-on;
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regulator-boot-on;
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regulator-state-mem {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <3000000>;
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};
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};
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vcca3v0_codec: LDO_REG5 {
|
|
|
|
regulator-name = "vcca3v0_codec";
|
|
|
|
regulator-min-microvolt = <3000000>;
|
|
|
|
regulator-max-microvolt = <3000000>;
|
|
|
|
regulator-always-on;
|
|
|
|
regulator-boot-on;
|
|
|
|
regulator-state-mem {
|
|
|
|
regulator-off-in-suspend;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
vcc_1v5: LDO_REG6 {
|
|
|
|
regulator-name = "vcc_1v5";
|
|
|
|
regulator-min-microvolt = <1500000>;
|
|
|
|
regulator-max-microvolt = <1500000>;
|
|
|
|
regulator-always-on;
|
|
|
|
regulator-boot-on;
|
|
|
|
regulator-state-mem {
|
|
|
|
regulator-on-in-suspend;
|
|
|
|
regulator-suspend-microvolt = <1500000>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
vcca1v8_codec: LDO_REG7 {
|
|
|
|
regulator-name = "vcca1v8_codec";
|
|
|
|
regulator-min-microvolt = <1800000>;
|
|
|
|
regulator-max-microvolt = <1800000>;
|
|
|
|
regulator-always-on;
|
|
|
|
regulator-boot-on;
|
|
|
|
regulator-state-mem {
|
|
|
|
regulator-off-in-suspend;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
vcc_3v0: LDO_REG8 {
|
|
|
|
regulator-name = "vcc_3v0";
|
|
|
|
regulator-min-microvolt = <3000000>;
|
|
|
|
regulator-max-microvolt = <3000000>;
|
|
|
|
regulator-always-on;
|
|
|
|
regulator-boot-on;
|
|
|
|
regulator-state-mem {
|
|
|
|
regulator-on-in-suspend;
|
|
|
|
regulator-suspend-microvolt = <3000000>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
vcc3v3_s3: SWITCH_REG1 {
|
|
|
|
regulator-name = "vcc3v3_s3";
|
|
|
|
regulator-always-on;
|
|
|
|
regulator-boot-on;
|
|
|
|
regulator-state-mem {
|
|
|
|
regulator-on-in-suspend;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
vcc3v3_s0: SWITCH_REG2 {
|
|
|
|
regulator-name = "vcc3v3_s0";
|
|
|
|
regulator-always-on;
|
|
|
|
regulator-boot-on;
|
|
|
|
regulator-state-mem {
|
|
|
|
regulator-off-in-suspend;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
vdd_cpu_b: regulator@40 {
|
|
|
|
compatible = "silergy,syr827";
|
|
|
|
reg = <0x40>;
|
|
|
|
fcs,suspend-voltage-selector = <1>;
|
|
|
|
regulator-name = "vdd_cpu_b";
|
|
|
|
regulator-min-microvolt = <712500>;
|
|
|
|
regulator-max-microvolt = <1500000>;
|
|
|
|
regulator-ramp-delay = <1000>;
|
|
|
|
regulator-always-on;
|
|
|
|
regulator-boot-on;
|
|
|
|
vin-supply = <&vcc5v0_sys>;
|
|
|
|
|
|
|
|
regulator-state-mem {
|
|
|
|
regulator-off-in-suspend;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
vdd_gpu: regulator@41 {
|
|
|
|
compatible = "silergy,syr828";
|
|
|
|
reg = <0x41>;
|
|
|
|
fcs,suspend-voltage-selector = <1>;
|
|
|
|
regulator-name = "vdd_gpu";
|
|
|
|
regulator-min-microvolt = <712500>;
|
|
|
|
regulator-max-microvolt = <1500000>;
|
|
|
|
regulator-ramp-delay = <1000>;
|
|
|
|
regulator-always-on;
|
|
|
|
regulator-boot-on;
|
|
|
|
vin-supply = <&vcc5v0_sys>;
|
|
|
|
|
|
|
|
regulator-state-mem {
|
|
|
|
regulator-off-in-suspend;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
2016-04-27 15:54:53 +08:00
|
|
|
&pwm0 {
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|
|
|
|
&pwm2 {
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|
|
|
|
&pwm3 {
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|
2016-05-13 15:12:04 -07:00
|
|
|
&sdhci {
|
|
|
|
bus-width = <8>;
|
|
|
|
mmc-hs400-1_8v;
|
|
|
|
mmc-hs400-enhanced-strobe;
|
|
|
|
non-removable;
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|
2016-08-19 11:24:29 +08:00
|
|
|
&pcie_phy {
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
&pcie0 {
|
2016-10-22 20:59:04 +08:00
|
|
|
ep-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>;
|
2016-08-19 11:24:29 +08:00
|
|
|
num-lanes = <4>;
|
|
|
|
pinctrl-names = "default";
|
2017-06-29 08:29:16 +08:00
|
|
|
pinctrl-0 = <&pcie_clkreqn_cpm>;
|
2016-08-19 11:24:29 +08:00
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
2016-07-22 15:00:46 +08:00
|
|
|
&u2phy0 {
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|
|
|
|
&u2phy0_host {
|
|
|
|
phy-supply = <&vcc5v0_host>;
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|
|
|
|
&u2phy1 {
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|
|
|
|
&u2phy1_host {
|
|
|
|
phy-supply = <&vcc5v0_host>;
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|
2016-04-27 15:54:53 +08:00
|
|
|
&uart2 {
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|
|
|
|
&usb_host0_ehci {
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|
|
|
|
&usb_host0_ohci {
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|
|
|
|
&usb_host1_ehci {
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|
|
|
|
&usb_host1_ohci {
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|
|
|
|
&pinctrl {
|
|
|
|
pmic {
|
|
|
|
pmic_int_l: pmic-int-l {
|
|
|
|
rockchip,pins =
|
2019-04-02 13:56:24 +02:00
|
|
|
<1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
|
2016-04-27 15:54:53 +08:00
|
|
|
};
|
|
|
|
};
|
2016-07-22 15:00:46 +08:00
|
|
|
|
|
|
|
usb2 {
|
|
|
|
vcc5v0_host_en: vcc5v0-host-en {
|
|
|
|
rockchip,pins =
|
2019-04-02 13:56:24 +02:00
|
|
|
<4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
|
2016-07-22 15:00:46 +08:00
|
|
|
};
|
|
|
|
};
|
2016-04-27 15:54:53 +08:00
|
|
|
};
|
2020-03-05 19:39:12 +08:00
|
|
|
|
|
|
|
&vopb {
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|
|
|
|
&vopb_mmu {
|
|
|
|
status = "okay";
|
|
|
|
};
|