2018-02-27 12:30:33 +01:00
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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2017-05-21 20:51:05 +02:00
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/*
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* Copyright (c) 2017 Andreas Färber
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*/
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/dts-v1/;
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#include "meson-gxbb.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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2020-12-03 06:00:20 +00:00
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#include <dt-bindings/sound/meson-aiu.h>
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2017-05-21 20:51:05 +02:00
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/ {
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compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
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2019-08-23 09:02:46 +02:00
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model = "FriendlyARM NanoPi K2";
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2017-05-21 20:51:05 +02:00
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aliases {
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serial0 = &uart_AO;
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2018-01-17 11:56:27 +01:00
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ethernet0 = ðmac;
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2017-05-21 20:51:05 +02:00
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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leds {
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compatible = "gpio-leds";
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arm64: dts: meson: fix leds subnodes name
Fix the leds subnode names to match (^led-[0-9a-f]$|led)
It fixes:
meson-g12b-a311d-khadas-vim3.dt.yaml: leds: 'red', 'white' do not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'
meson-g12b-s922x-khadas-vim3.dt.yaml: leds: 'red', 'white' do not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'
meson-g12b-odroid-n2.dt.yaml: leds: 'blue' does not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'
meson-gxbb-nanopi-k2.dt.yaml: leds: 'stat' does not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'
meson-gxbb-nexbox-a95x.dt.yaml: leds: 'blue' does not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'
meson-gxbb-odroidc2.dt.yaml: leds: 'blue' does not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'
meson-gxbb-vega-s95-pro.dt.yaml: leds: 'blue' does not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'
meson-gxbb-vega-s95-meta.dt.yaml: leds: 'blue' does not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'
meson-gxbb-vega-s95-telos.dt.yaml: leds: 'blue' does not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'
meson-gxbb-wetek-hub.dt.yaml: leds: 'system' does not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'
meson-gxbb-wetek-play2.dt.yaml: leds: 'ethernet', 'system', 'wifi' do not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'
meson-gxl-s905x-libretech-cc.dt.yaml: leds: 'blue', 'system' do not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'
meson-gxl-s905d-libretech-pc.dt.yaml: leds: 'blue', 'green' do not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'
meson-gxm-rbox-pro.dt.yaml: leds: 'blue', 'red' do not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'
meson-gxm-s912-libretech-pc.dt.yaml: leds: 'blue', 'green' do not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'
meson-sm1-sei610.dt.yaml: leds: 'bluetooth' does not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'
meson-sm1-khadas-vim3l.dt.yaml: leds: 'red', 'white' do not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200326165958.19274-6-narmstrong@baylibre.com
2020-03-26 17:59:58 +01:00
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led-stat {
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2017-05-21 20:51:05 +02:00
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label = "nanopi-k2:blue:stat";
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gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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panic-indicator;
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};
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};
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vdd_5v: regulator-vdd-5v {
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compatible = "regulator-fixed";
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regulator-name = "VDD_5V";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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vddio_ao18: regulator-vddio-ao18 {
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compatible = "regulator-fixed";
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regulator-name = "VDDIO_AO18";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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vddio_ao3v3: regulator-vddio-ao3v3 {
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compatible = "regulator-fixed";
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regulator-name = "VDDIO_AO3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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vddio_tf: regulator-vddio-tf {
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compatible = "regulator-gpio";
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regulator-name = "VDDIO_TF";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
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gpios-states = <0>;
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states = <3300000 0>,
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<1800000 1>;
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2017-08-31 15:52:21 +02:00
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regulator-settling-time-up-us = <100>;
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regulator-settling-time-down-us = <5000>;
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2017-05-21 20:51:05 +02:00
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};
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wifi_32k: wifi-32k {
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compatible = "pwm-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
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};
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sdio_pwrseq: sdio-pwrseq {
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compatible = "mmc-pwrseq-simple";
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reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
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clocks = <&wifi_32k>;
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clock-names = "ext_clock";
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};
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vcc1v8: regulator-vcc1v8 {
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compatible = "regulator-fixed";
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regulator-name = "VCC1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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vcc3v3: regulator-vcc3v3 {
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compatible = "regulator-fixed";
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regulator-name = "VCC3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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emmc_pwrseq: emmc-pwrseq {
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compatible = "mmc-pwrseq-emmc";
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reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
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};
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2018-06-26 09:40:55 +02:00
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/* CVBS is available on CON1 pin 36, disabled by default */
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cvbs-connector {
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compatible = "composite-video-connector";
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status = "disabled";
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port {
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cvbs_connector_in: endpoint {
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remote-endpoint = <&cvbs_vdac_out>;
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};
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};
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};
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hdmi-connector {
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compatible = "hdmi-connector";
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type = "a";
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port {
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hdmi_connector_in: endpoint {
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remote-endpoint = <&hdmi_tx_tmds_out>;
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};
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};
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};
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2020-12-03 06:00:20 +00:00
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sound {
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compatible = "amlogic,gx-sound-card";
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2021-01-01 06:37:37 +00:00
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model = "NANOPI-K2";
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2024-08-28 15:53:56 +02:00
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clocks = <&clkc CLKID_MPLL0>,
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<&clkc CLKID_MPLL1>,
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<&clkc CLKID_MPLL2>;
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2020-12-03 06:00:20 +00:00
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assigned-clocks = <&clkc CLKID_MPLL0>,
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<&clkc CLKID_MPLL1>,
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<&clkc CLKID_MPLL2>;
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assigned-clock-parents = <0>, <0>, <0>;
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assigned-clock-rates = <294912000>,
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<270950400>,
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<393216000>;
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dai-link-0 {
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sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
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};
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dai-link-1 {
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sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
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dai-format = "i2s";
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mclk-fs = <256>;
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codec-0 {
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sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
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};
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};
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dai-link-2 {
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sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
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codec-0 {
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sound-dai = <&hdmi_tx>;
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};
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};
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};
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};
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&aiu {
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status = "okay";
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2018-06-26 09:40:55 +02:00
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};
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&cec_AO {
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status = "okay";
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pinctrl-0 = <&ao_cec_pins>;
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pinctrl-names = "default";
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hdmi-phandle = <&hdmi_tx>;
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};
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&cvbs_vdac_port {
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cvbs_vdac_out: endpoint {
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remote-endpoint = <&cvbs_connector_in>;
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};
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2017-05-21 20:51:05 +02:00
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};
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ðmac {
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status = "okay";
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pinctrl-0 = <ð_rgmii_pins>;
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pinctrl-names = "default";
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phy-handle = <ð_phy0>;
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phy-mode = "rgmii";
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amlogic,tx-delay-ns = <2>;
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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eth_phy0: ethernet-phy@0 {
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/* Realtek RTL8211F (0x001cc916) */
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reg = <0>;
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arm64: dts: meson: use the generic Ethernet PHY reset GPIO bindings
The snps,reset-gpio bindings are deprecated in favour of the generic
"Ethernet PHY reset" bindings.
Replace snps,reset-gpio from the ðmac node with reset-gpios in the
ethernet-phy node. The old snps,reset-active-low property is now encoded
directly as GPIO flag inside the reset-gpios property.
snps,reset-delays-us is converted to reset-assert-us and
reset-deassert-us. reset-assert-us is the second cell from
snps,reset-delays-us while reset-deassert-us was the third cell.
Instead of blindly copying the old values (which seems strange since
they gave the PHY one second to come out of reset) over this also
updates the delays based on the datasheets:
- the Realtek RTL8211F PHY needs a 10ms assert delay (the datasheet
mentions: "For a complete PHY reset, this pin must be asserted low
for at least 10ms") and a 30ms deassert delay (the datasheet
mentions: "Wait for a further 30ms (for internal circuits settling
time) before accessing the PHY register". This applies to the
following boards: GXBB NanoPi K2, GXBB Odroid-C2, GXBB Vega S95
variants, GXBB Wetek variants, GXL P230, GXM Khadas VIM2, GXM Nexbox
A1, GXM Q200, GXM RBox Pro boards.
- the ICPlus IP101GR PHY needs a 10ms assert delay (the datasheet
mentions: "Trst | Reset period | 10ms") and a deassert delay of 10ms
as well (the datasheet mentions: "Tclk_MII_rdy | MII/RMII clock
output ready after reset released | 10ms"). This applies to the GXBB
Nexbox A95X board.
- the Micrel KSZ9031 seems to require a 100us delay but use the same
(seemingly safe) values from RTL8211F due to lack of a board to verify
this. This applies to the GXBB P200 board.
The GXBB P201 board is left out from this conversion because it doesn't
have a dedicated PHY node (because it's not clear which PHY is used on
that board).
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-06-15 12:38:31 +02:00
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reset-assert-us = <10000>;
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2020-12-07 18:58:00 +01:00
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reset-deassert-us = <80000>;
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arm64: dts: meson: use the generic Ethernet PHY reset GPIO bindings
The snps,reset-gpio bindings are deprecated in favour of the generic
"Ethernet PHY reset" bindings.
Replace snps,reset-gpio from the ðmac node with reset-gpios in the
ethernet-phy node. The old snps,reset-active-low property is now encoded
directly as GPIO flag inside the reset-gpios property.
snps,reset-delays-us is converted to reset-assert-us and
reset-deassert-us. reset-assert-us is the second cell from
snps,reset-delays-us while reset-deassert-us was the third cell.
Instead of blindly copying the old values (which seems strange since
they gave the PHY one second to come out of reset) over this also
updates the delays based on the datasheets:
- the Realtek RTL8211F PHY needs a 10ms assert delay (the datasheet
mentions: "For a complete PHY reset, this pin must be asserted low
for at least 10ms") and a 30ms deassert delay (the datasheet
mentions: "Wait for a further 30ms (for internal circuits settling
time) before accessing the PHY register". This applies to the
following boards: GXBB NanoPi K2, GXBB Odroid-C2, GXBB Vega S95
variants, GXBB Wetek variants, GXL P230, GXM Khadas VIM2, GXM Nexbox
A1, GXM Q200, GXM RBox Pro boards.
- the ICPlus IP101GR PHY needs a 10ms assert delay (the datasheet
mentions: "Trst | Reset period | 10ms") and a deassert delay of 10ms
as well (the datasheet mentions: "Tclk_MII_rdy | MII/RMII clock
output ready after reset released | 10ms"). This applies to the GXBB
Nexbox A95X board.
- the Micrel KSZ9031 seems to require a 100us delay but use the same
(seemingly safe) values from RTL8211F due to lack of a board to verify
this. This applies to the GXBB P200 board.
The GXBB P201 board is left out from this conversion because it doesn't
have a dedicated PHY node (because it's not clear which PHY is used on
that board).
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-06-15 12:38:31 +02:00
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reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
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2017-10-19 14:01:43 +02:00
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interrupt-parent = <&gpio_intc>;
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2017-12-02 22:40:36 +01:00
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/* MAC_INTR on GPIOZ_15 */
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2017-10-19 14:01:43 +02:00
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interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
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2017-05-21 20:51:05 +02:00
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};
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};
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};
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2018-06-26 09:40:55 +02:00
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&hdmi_tx {
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status = "okay";
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pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
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pinctrl-names = "default";
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};
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&hdmi_tx_tmds_port {
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hdmi_tx_tmds_out: endpoint {
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remote-endpoint = <&hdmi_connector_in>;
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};
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};
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2017-05-21 20:51:05 +02:00
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&ir {
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status = "okay";
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pinctrl-0 = <&remote_input_ao_pins>;
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pinctrl-names = "default";
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};
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2018-11-07 11:45:48 +01:00
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&gpio_ao {
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2017-07-28 15:54:44 +02:00
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gpio-line-names = "UART TX", "UART RX", "Power Control", "Power Key In",
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"VCCK En", "CON1 Header Pin31",
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"I2S Header Pin6", "IR In", "I2S Header Pin7",
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"I2S Header Pin3", "I2S Header Pin4",
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2017-09-21 19:14:47 +02:00
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"I2S Header Pin5", "HDMI CEC", "SYS LED",
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/* GPIO_TEST_N */
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"";
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2017-07-28 15:54:44 +02:00
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};
|
|
|
|
|
2018-11-07 11:45:48 +01:00
|
|
|
&gpio {
|
2017-07-28 15:54:44 +02:00
|
|
|
gpio-line-names = /* Bank GPIOZ */
|
|
|
|
"Eth MDIO", "Eth MDC", "Eth RGMII RX Clk",
|
|
|
|
"Eth RX DV", "Eth RX D0", "Eth RX D1", "Eth RX D2",
|
|
|
|
"Eth RX D3", "Eth RGMII TX Clk", "Eth TX En",
|
|
|
|
"Eth TX D0", "Eth TX D1", "Eth TX D2", "Eth TX D3",
|
|
|
|
"Eth PHY nRESET", "Eth PHY Intc",
|
|
|
|
/* Bank GPIOH */
|
|
|
|
"HDMI HPD", "HDMI DDC SDA", "HDMI DDC SCL",
|
|
|
|
"CON1 Header Pin33",
|
|
|
|
/* Bank BOOT */
|
|
|
|
"eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", "eMMC D4",
|
|
|
|
"eMMC D5", "eMMC D6", "eMMC D7", "eMMC Clk",
|
|
|
|
"eMMC Reset", "eMMC CMD",
|
|
|
|
"", "", "", "", "eMMC DS",
|
|
|
|
"", "",
|
|
|
|
/* Bank CARD */
|
|
|
|
"SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
|
|
|
|
"SDCard D3", "SDCard D2", "SDCard Det",
|
|
|
|
/* Bank GPIODV */
|
|
|
|
"", "", "", "", "", "", "", "", "", "", "", "", "",
|
|
|
|
"", "", "", "", "", "", "", "", "", "", "",
|
|
|
|
"I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK",
|
|
|
|
"VDDEE Regulator", "VCCK Regulator",
|
|
|
|
/* Bank GPIOY */
|
|
|
|
"CON1 Header Pin7", "CON1 Header Pin11",
|
|
|
|
"CON1 Header Pin13", "CON1 Header Pin15",
|
|
|
|
"CON1 Header Pin18", "CON1 Header Pin19",
|
|
|
|
"CON1 Header Pin22", "CON1 Header Pin21",
|
|
|
|
"CON1 Header Pin24", "CON1 Header Pin23",
|
|
|
|
"CON1 Header Pin26", "CON1 Header Pin29",
|
|
|
|
"CON1 Header Pin32", "CON1 Header Pin8",
|
|
|
|
"CON1 Header Pin10", "CON1 Header Pin16",
|
|
|
|
"CON1 Header Pin12",
|
|
|
|
/* Bank GPIOX */
|
|
|
|
"WIFI SDIO D0", "WIFI SDIO D1", "WIFI SDIO D2",
|
|
|
|
"WIFI SDIO D3", "WIFI SDIO CLK", "WIFI SDIO CMD",
|
|
|
|
"WIFI Power Enable", "WIFI WAKE HOST",
|
|
|
|
"Bluetooth PCM DOUT", "Bluetooth PCM DIN",
|
|
|
|
"Bluetooth PCM SYNC", "Bluetooth PCM CLK",
|
|
|
|
"Bluetooth UART TX", "Bluetooth UART RX",
|
|
|
|
"Bluetooth UART CTS", "Bluetooth UART RTS",
|
|
|
|
"", "", "", "WIFI 32K", "Bluetooth Enable",
|
2017-09-21 19:14:47 +02:00
|
|
|
"Bluetooth WAKE HOST", "",
|
2017-07-28 15:54:44 +02:00
|
|
|
/* Bank GPIOCLK */
|
2017-09-21 19:14:47 +02:00
|
|
|
"", "CON1 Header Pin35", "", "";
|
2017-07-28 15:54:44 +02:00
|
|
|
};
|
|
|
|
|
2017-05-21 20:51:05 +02:00
|
|
|
&pwm_ef {
|
|
|
|
status = "okay";
|
|
|
|
pinctrl-0 = <&pwm_e_pins>;
|
|
|
|
pinctrl-names = "default";
|
|
|
|
};
|
|
|
|
|
|
|
|
&saradc {
|
|
|
|
status = "okay";
|
|
|
|
vref-supply = <&vddio_ao18>;
|
|
|
|
};
|
|
|
|
|
|
|
|
/* SDIO */
|
|
|
|
&sd_emmc_a {
|
|
|
|
status = "okay";
|
|
|
|
pinctrl-0 = <&sdio_pins>, <&sdio_irq_pins>;
|
2017-08-31 15:52:20 +02:00
|
|
|
pinctrl-1 = <&sdio_clk_gate_pins>;
|
|
|
|
pinctrl-names = "default", "clk-gate";
|
2017-05-21 20:51:05 +02:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
bus-width = <4>;
|
|
|
|
cap-sd-highspeed;
|
2019-04-18 14:27:12 +02:00
|
|
|
max-frequency = <50000000>;
|
2017-05-21 20:51:05 +02:00
|
|
|
|
|
|
|
non-removable;
|
|
|
|
disable-wp;
|
|
|
|
|
2019-08-29 17:23:32 +02:00
|
|
|
/* WiFi firmware requires power to be kept while in suspend */
|
|
|
|
keep-power-in-suspend;
|
|
|
|
|
2017-05-21 20:51:05 +02:00
|
|
|
mmc-pwrseq = <&sdio_pwrseq>;
|
|
|
|
|
|
|
|
vmmc-supply = <&vddio_ao3v3>;
|
|
|
|
vqmmc-supply = <&vddio_ao18>;
|
|
|
|
|
|
|
|
brcmf: wifi@1 {
|
|
|
|
compatible = "brcm,bcm4329-fmac";
|
|
|
|
reg = <1>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
/* SD */
|
|
|
|
&sd_emmc_b {
|
|
|
|
status = "okay";
|
|
|
|
pinctrl-0 = <&sdcard_pins>;
|
2017-08-31 15:52:20 +02:00
|
|
|
pinctrl-1 = <&sdcard_clk_gate_pins>;
|
|
|
|
pinctrl-names = "default", "clk-gate";
|
2017-05-21 20:51:05 +02:00
|
|
|
|
|
|
|
bus-width = <4>;
|
|
|
|
cap-sd-highspeed;
|
2017-08-31 15:52:25 +02:00
|
|
|
sd-uhs-sdr12;
|
|
|
|
sd-uhs-sdr25;
|
|
|
|
sd-uhs-sdr50;
|
2019-05-13 15:05:07 +02:00
|
|
|
sd-uhs-ddr50;
|
2019-04-18 14:27:12 +02:00
|
|
|
max-frequency = <100000000>;
|
2017-05-21 20:51:05 +02:00
|
|
|
disable-wp;
|
|
|
|
|
2019-01-14 15:44:21 +01:00
|
|
|
cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;
|
2017-05-21 20:51:05 +02:00
|
|
|
|
|
|
|
vmmc-supply = <&vddio_ao3v3>;
|
|
|
|
vqmmc-supply = <&vddio_tf>;
|
|
|
|
};
|
|
|
|
|
|
|
|
/* eMMC */
|
|
|
|
&sd_emmc_c {
|
|
|
|
status = "disabled";
|
2017-10-03 17:24:42 +02:00
|
|
|
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
|
2017-08-31 15:52:20 +02:00
|
|
|
pinctrl-1 = <&emmc_clk_gate_pins>;
|
|
|
|
pinctrl-names = "default", "clk-gate";
|
2017-05-21 20:51:05 +02:00
|
|
|
|
|
|
|
bus-width = <8>;
|
|
|
|
max-frequency = <200000000>;
|
|
|
|
non-removable;
|
|
|
|
disable-wp;
|
|
|
|
cap-mmc-highspeed;
|
|
|
|
mmc-ddr-1_8v;
|
|
|
|
mmc-hs200-1_8v;
|
|
|
|
|
|
|
|
mmc-pwrseq = <&emmc_pwrseq>;
|
|
|
|
vmmc-supply = <&vcc3v3>;
|
|
|
|
vqmmc-supply = <&vcc1v8>;
|
|
|
|
};
|
|
|
|
|
|
|
|
/* DBG_UART */
|
|
|
|
&uart_AO {
|
|
|
|
status = "okay";
|
|
|
|
pinctrl-0 = <&uart_ao_a_pins>;
|
|
|
|
pinctrl-names = "default";
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Bluetooth on AP6212 */
|
|
|
|
&uart_A {
|
2021-07-12 21:59:19 +08:00
|
|
|
status = "okay";
|
2017-05-21 20:51:05 +02:00
|
|
|
pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
|
|
|
|
pinctrl-names = "default";
|
2021-07-12 21:59:19 +08:00
|
|
|
uart-has-rtscts;
|
|
|
|
|
|
|
|
bluetooth {
|
|
|
|
compatible = "brcm,bcm43438-bt";
|
|
|
|
clocks = <&wifi_32k>;
|
|
|
|
clock-names = "lpo";
|
|
|
|
vbat-supply = <&vddio_ao3v3>;
|
|
|
|
vddio-supply = <&vddio_ao18>;
|
|
|
|
host-wakeup-gpios = <&gpio GPIOX_21 GPIO_ACTIVE_HIGH>;
|
|
|
|
shutdown-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>;
|
|
|
|
};
|
2017-05-21 20:51:05 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
/* 40-pin CON1 */
|
|
|
|
&uart_C {
|
|
|
|
status = "disabled";
|
|
|
|
pinctrl-0 = <&uart_c_pins>;
|
|
|
|
pinctrl-names = "default";
|
|
|
|
};
|
|
|
|
|
|
|
|
&usb0_phy {
|
|
|
|
status = "okay";
|
|
|
|
phy-supply = <&vdd_5v>;
|
|
|
|
};
|
|
|
|
|
|
|
|
&usb1_phy {
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|
|
|
|
&usb0 {
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|
|
|
|
&usb1 {
|
|
|
|
status = "okay";
|
|
|
|
};
|