2020-01-19 20:11:43 +01:00
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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2020-05-13 20:10:19 +02:00
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* Copyright (C) 2019-2020 Marek Vasut <marex@denx.de>
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2020-01-19 20:11:43 +01:00
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*/
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#include "stm32mp15-pinctrl.dtsi"
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#include "stm32mp15xxaa-pinctrl.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/mfd/st,stpmic1.h>
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/ {
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2020-07-29 18:51:40 +02:00
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aliases {
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ethernet0 = ðernet0;
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2020-10-08 21:38:00 +02:00
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ethernet1 = &ksz8851;
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2021-06-20 20:54:21 +02:00
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rtc0 = &hwrtc;
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rtc1 = &rtc;
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2024-11-06 00:29:44 +01:00
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serial0 = &uart4;
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2024-12-13 23:36:25 +01:00
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serial1 = &uart8;
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serial2 = &usart3;
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2024-11-06 00:29:44 +01:00
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};
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chosen {
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stdout-path = "serial0:115200n8";
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2020-07-29 18:51:40 +02:00
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};
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2020-01-19 20:11:43 +01:00
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memory@c0000000 {
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device_type = "memory";
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reg = <0xC0000000 0x40000000>;
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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mcuram2: mcuram2@10000000 {
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compatible = "shared-dma-pool";
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reg = <0x10000000 0x40000>;
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no-map;
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};
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vdev0vring0: vdev0vring0@10040000 {
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compatible = "shared-dma-pool";
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reg = <0x10040000 0x1000>;
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no-map;
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};
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vdev0vring1: vdev0vring1@10041000 {
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compatible = "shared-dma-pool";
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reg = <0x10041000 0x1000>;
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no-map;
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};
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vdev0buffer: vdev0buffer@10042000 {
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compatible = "shared-dma-pool";
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reg = <0x10042000 0x4000>;
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no-map;
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};
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mcuram: mcuram@30000000 {
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compatible = "shared-dma-pool";
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reg = <0x30000000 0x40000>;
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no-map;
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};
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retram: retram@38000000 {
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compatible = "shared-dma-pool";
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reg = <0x38000000 0x10000>;
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no-map;
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};
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};
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2020-07-29 18:51:40 +02:00
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ethernet_vio: vioregulator {
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compatible = "regulator-fixed";
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regulator-name = "vio";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpiog 3 GPIO_ACTIVE_LOW>;
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regulator-always-on;
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regulator-boot-on;
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2020-10-29 20:46:17 +01:00
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vin-supply = <&vdd>;
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2020-07-29 18:51:40 +02:00
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};
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2020-01-19 20:11:43 +01:00
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};
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&adc {
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vdd-supply = <&vdd>;
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vdda-supply = <&vdda>;
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vref-supply = <&vdda>;
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status = "okay";
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2023-05-30 14:45:37 +02:00
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};
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2020-01-19 20:11:43 +01:00
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2023-05-30 14:45:37 +02:00
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&adc1 {
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channel@0 {
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reg = <0>;
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st,min-sample-time-ns = <5000>;
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2020-01-19 20:11:43 +01:00
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};
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2023-05-30 14:45:37 +02:00
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};
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2020-01-19 20:11:43 +01:00
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2023-05-30 14:45:37 +02:00
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&adc2 {
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channel@1 {
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reg = <1>;
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st,min-sample-time-ns = <5000>;
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2020-01-19 20:11:43 +01:00
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};
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};
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2021-03-25 22:45:33 +01:00
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&crc1 {
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status = "okay";
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};
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2020-01-19 20:11:43 +01:00
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&dac {
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pinctrl-names = "default";
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pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
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vref-supply = <&vdda>;
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status = "okay";
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dac1: dac@1 {
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status = "okay";
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};
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dac2: dac@2 {
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status = "okay";
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};
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};
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&dts {
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status = "okay";
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};
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2020-07-29 18:51:40 +02:00
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ðernet0 {
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status = "okay";
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2022-01-18 21:29:58 +01:00
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pinctrl-0 = <ðernet0_rmii_pins_c &mco2_pins_a>;
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pinctrl-1 = <ðernet0_rmii_sleep_pins_c &mco2_sleep_pins_a>;
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2020-07-29 18:51:40 +02:00
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pinctrl-names = "default", "sleep";
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phy-mode = "rmii";
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max-speed = <100>;
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phy-handle = <&phy0>;
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2022-09-27 00:44:37 +02:00
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mdio {
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2020-07-29 18:51:40 +02:00
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy0: ethernet-phy@1 {
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reg = <1>;
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ARM: dts: stm32: Rework LAN8710Ai PHY reset on DHCOM SoM
The Microchip LAN8710Ai PHY requires XTAL1/CLKIN external clock to be
enabled when the nRST is toggled according to datasheet Microchip
LAN8710A/LAN8710Ai DS00002164B page 35 section 3.8.5.1 Hardware Reset:
"
A Hardware reset is asserted by driving the nRST input pin low. When
driven, nRST should be held low for the minimum time detailed in
Section 5.5.3, "Power-On nRST & Configuration Strap Timing," on page
59 to ensure a proper transceiver reset. During a Hardware reset, an
external clock must be supplied to the XTAL1/CLKIN signal.
"
This is accidentally fulfilled in the current setup, where ETHCK_K is used
to supply both PHY XTAL1/CLKIN and is also fed back through eth_clk_fb to
supply ETHRX clock of the DWMAC. Hence, the DWMAC enables ETHRX clock,
that has ETHCK_K as parent, so ETHCK_K clock are also enabled, and then
the PHY reset toggles.
However, this is not always the case, e.g. in case the PHY XTAL1/CLKIN
clock are supplied by some other clock source than ETHCK_K or in case
ETHRX clock are not supplied by ETHCK_K. In the later case, ETHCK_K would
be kept disabled, while ETHRX clock would be enabled, so the PHY would
not be receiving XTAL1/CLKIN clock and the reset would fail.
Improve the DT by adding the PHY clock phandle into the PHY node, which
then also requires moving the PHY reset GPIO specifier in the same place
and that then also requires correct PHY reset GPIO timing, so add that
too.
A brief note regarding the timing, the datasheet says the reset should
stay asserted for at least 100uS and software should wait at least 200nS
after deassertion. Set both delays to 500uS which should be plenty.
Fixes: 34e0c7847dcf ("ARM: dts: stm32: Add DH Electronics DHCOM STM32MP1 SoM and PDK2 board")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-04-09 01:00:01 +02:00
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/* LAN8710Ai */
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compatible = "ethernet-phy-id0007.c0f0",
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"ethernet-phy-ieee802.3-c22";
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2022-01-18 21:29:58 +01:00
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clocks = <&rcc CK_MCO2>;
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ARM: dts: stm32: Rework LAN8710Ai PHY reset on DHCOM SoM
The Microchip LAN8710Ai PHY requires XTAL1/CLKIN external clock to be
enabled when the nRST is toggled according to datasheet Microchip
LAN8710A/LAN8710Ai DS00002164B page 35 section 3.8.5.1 Hardware Reset:
"
A Hardware reset is asserted by driving the nRST input pin low. When
driven, nRST should be held low for the minimum time detailed in
Section 5.5.3, "Power-On nRST & Configuration Strap Timing," on page
59 to ensure a proper transceiver reset. During a Hardware reset, an
external clock must be supplied to the XTAL1/CLKIN signal.
"
This is accidentally fulfilled in the current setup, where ETHCK_K is used
to supply both PHY XTAL1/CLKIN and is also fed back through eth_clk_fb to
supply ETHRX clock of the DWMAC. Hence, the DWMAC enables ETHRX clock,
that has ETHCK_K as parent, so ETHCK_K clock are also enabled, and then
the PHY reset toggles.
However, this is not always the case, e.g. in case the PHY XTAL1/CLKIN
clock are supplied by some other clock source than ETHCK_K or in case
ETHRX clock are not supplied by ETHCK_K. In the later case, ETHCK_K would
be kept disabled, while ETHRX clock would be enabled, so the PHY would
not be receiving XTAL1/CLKIN clock and the reset would fail.
Improve the DT by adding the PHY clock phandle into the PHY node, which
then also requires moving the PHY reset GPIO specifier in the same place
and that then also requires correct PHY reset GPIO timing, so add that
too.
A brief note regarding the timing, the datasheet says the reset should
stay asserted for at least 100uS and software should wait at least 200nS
after deassertion. Set both delays to 500uS which should be plenty.
Fixes: 34e0c7847dcf ("ARM: dts: stm32: Add DH Electronics DHCOM STM32MP1 SoM and PDK2 board")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-04-09 01:00:01 +02:00
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reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
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reset-assert-us = <500>;
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reset-deassert-us = <500>;
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2021-07-21 20:12:53 +02:00
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smsc,disable-energy-detect;
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2020-10-08 21:36:18 +02:00
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interrupt-parent = <&gpioi>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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2020-07-29 18:51:40 +02:00
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};
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};
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};
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2020-10-08 21:38:00 +02:00
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&fmc {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&fmc_pins_b>;
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pinctrl-1 = <&fmc_sleep_pins_b>;
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status = "okay";
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2021-06-10 02:25:51 +02:00
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ksz8851: ethernet@1,0 {
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2020-10-08 21:38:00 +02:00
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compatible = "micrel,ks8851-mll";
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reg = <1 0x0 0x2>, <1 0x2 0x20000>;
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interrupt-parent = <&gpioc>;
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interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
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bank-width = <2>;
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/* Timing values are in nS */
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st,fmc2-ebi-cs-mux-enable;
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st,fmc2-ebi-cs-transaction-type = <4>;
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st,fmc2-ebi-cs-buswidth = <16>;
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st,fmc2-ebi-cs-address-setup-ns = <5>;
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st,fmc2-ebi-cs-address-hold-ns = <5>;
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st,fmc2-ebi-cs-bus-turnaround-ns = <5>;
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st,fmc2-ebi-cs-data-setup-ns = <45>;
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st,fmc2-ebi-cs-data-hold-ns = <1>;
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st,fmc2-ebi-cs-write-address-setup-ns = <5>;
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st,fmc2-ebi-cs-write-address-hold-ns = <5>;
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st,fmc2-ebi-cs-write-bus-turnaround-ns = <5>;
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st,fmc2-ebi-cs-write-data-setup-ns = <45>;
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st,fmc2-ebi-cs-write-data-hold-ns = <1>;
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};
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};
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2021-03-29 21:36:11 +02:00
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&gpioa {
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gpio-line-names = "", "", "", "",
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"", "", "DHCOM-K", "",
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"", "", "", "",
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"", "", "", "";
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};
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&gpiob {
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gpio-line-names = "", "", "", "",
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"", "", "", "",
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"DHCOM-Q", "", "", "",
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"", "", "", "";
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};
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2020-10-08 21:38:00 +02:00
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&gpioc {
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2021-03-29 21:36:11 +02:00
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gpio-line-names = "", "", "", "",
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"", "", "DHCOM-E", "",
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"", "", "", "",
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"", "", "", "";
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2020-10-08 21:38:00 +02:00
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};
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2021-03-29 21:36:11 +02:00
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&gpiod {
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gpio-line-names = "", "", "", "",
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"", "", "DHCOM-B", "",
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"", "", "", "DHCOM-F",
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"DHCOM-D", "", "", "";
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};
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&gpioe {
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gpio-line-names = "", "", "", "",
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"", "", "DHCOM-P", "",
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"", "", "", "",
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"", "", "", "";
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};
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&gpiof {
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gpio-line-names = "", "", "", "DHCOM-A",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "";
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};
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&gpiog {
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gpio-line-names = "DHCOM-C", "", "", "",
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"", "", "", "",
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"DHCOM-L", "", "", "",
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"", "", "", "";
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};
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&gpioh {
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gpio-line-names = "", "", "", "",
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"", "", "", "DHCOM-N",
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"DHCOM-J", "DHCOM-W", "DHCOM-V", "DHCOM-U",
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"DHCOM-T", "", "DHCOM-S", "";
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};
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&gpioi {
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gpio-line-names = "DHCOM-G", "DHCOM-O", "DHCOM-H", "DHCOM-I",
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"DHCOM-R", "DHCOM-M", "", "",
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"", "", "", "",
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"", "", "", "";
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};
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2020-01-19 20:11:43 +01:00
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&i2c4 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c4_pins_a>;
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|
|
i2c-scl-rising-time-ns = <185>;
|
|
|
|
|
i2c-scl-falling-time-ns = <20>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
/* spare dmas for other usage */
|
|
|
|
|
/delete-property/dmas;
|
|
|
|
|
/delete-property/dma-names;
|
|
|
|
|
|
2021-06-20 20:54:21 +02:00
|
|
|
hwrtc: rtc@32 {
|
2020-01-19 20:11:43 +01:00
|
|
|
compatible = "microcrystal,rv8803";
|
|
|
|
|
reg = <0x32>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmic: stpmic@33 {
|
|
|
|
|
compatible = "st,stpmic1";
|
|
|
|
|
reg = <0x33>;
|
|
|
|
|
interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
|
|
|
|
|
regulators {
|
|
|
|
|
compatible = "st,stpmic1-regulators";
|
|
|
|
|
ldo1-supply = <&v3v3>;
|
|
|
|
|
ldo2-supply = <&v3v3>;
|
|
|
|
|
ldo3-supply = <&vdd_ddr>;
|
|
|
|
|
ldo5-supply = <&v3v3>;
|
|
|
|
|
ldo6-supply = <&v3v3>;
|
|
|
|
|
pwr_sw1-supply = <&bst_out>;
|
|
|
|
|
pwr_sw2-supply = <&bst_out>;
|
|
|
|
|
|
|
|
|
|
vddcore: buck1 {
|
|
|
|
|
regulator-name = "vddcore";
|
|
|
|
|
regulator-min-microvolt = <800000>;
|
|
|
|
|
regulator-max-microvolt = <1350000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-initial-mode = <0>;
|
|
|
|
|
regulator-over-current-protection;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vdd_ddr: buck2 {
|
|
|
|
|
regulator-name = "vdd_ddr";
|
|
|
|
|
regulator-min-microvolt = <1350000>;
|
|
|
|
|
regulator-max-microvolt = <1350000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-initial-mode = <0>;
|
|
|
|
|
regulator-over-current-protection;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vdd: buck3 {
|
|
|
|
|
regulator-name = "vdd";
|
|
|
|
|
regulator-min-microvolt = <3300000>;
|
|
|
|
|
regulator-max-microvolt = <3300000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
st,mask-reset;
|
|
|
|
|
regulator-initial-mode = <0>;
|
|
|
|
|
regulator-over-current-protection;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
v3v3: buck4 {
|
|
|
|
|
regulator-name = "v3v3";
|
|
|
|
|
regulator-min-microvolt = <3300000>;
|
|
|
|
|
regulator-max-microvolt = <3300000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-over-current-protection;
|
|
|
|
|
regulator-initial-mode = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vdda: ldo1 {
|
|
|
|
|
regulator-name = "vdda";
|
2020-10-29 20:46:52 +01:00
|
|
|
regulator-always-on;
|
2020-01-19 20:11:43 +01:00
|
|
|
regulator-min-microvolt = <2900000>;
|
|
|
|
|
regulator-max-microvolt = <2900000>;
|
|
|
|
|
interrupts = <IT_CURLIM_LDO1 0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
v2v8: ldo2 {
|
|
|
|
|
regulator-name = "v2v8";
|
|
|
|
|
regulator-min-microvolt = <2800000>;
|
|
|
|
|
regulator-max-microvolt = <2800000>;
|
|
|
|
|
interrupts = <IT_CURLIM_LDO2 0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vtt_ddr: ldo3 {
|
|
|
|
|
regulator-name = "vtt_ddr";
|
|
|
|
|
regulator-min-microvolt = <500000>;
|
|
|
|
|
regulator-max-microvolt = <750000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-over-current-protection;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vdd_usb: ldo4 {
|
|
|
|
|
regulator-name = "vdd_usb";
|
|
|
|
|
interrupts = <IT_CURLIM_LDO4 0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vdd_sd: ldo5 {
|
|
|
|
|
regulator-name = "vdd_sd";
|
|
|
|
|
regulator-min-microvolt = <2900000>;
|
|
|
|
|
regulator-max-microvolt = <2900000>;
|
|
|
|
|
interrupts = <IT_CURLIM_LDO5 0>;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
v1v8: ldo6 {
|
|
|
|
|
regulator-name = "v1v8";
|
|
|
|
|
regulator-min-microvolt = <1800000>;
|
|
|
|
|
regulator-max-microvolt = <1800000>;
|
|
|
|
|
interrupts = <IT_CURLIM_LDO6 0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vref_ddr: vref_ddr {
|
|
|
|
|
regulator-name = "vref_ddr";
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
bst_out: boost {
|
|
|
|
|
regulator-name = "bst_out";
|
|
|
|
|
interrupts = <IT_OCP_BOOST 0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vbus_otg: pwr_sw1 {
|
|
|
|
|
regulator-name = "vbus_otg";
|
|
|
|
|
interrupts = <IT_OCP_OTG 0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vbus_sw: pwr_sw2 {
|
|
|
|
|
regulator-name = "vbus_sw";
|
|
|
|
|
interrupts = <IT_OCP_SWOUT 0>;
|
2021-04-15 12:10:33 +02:00
|
|
|
regulator-active-discharge = <1>;
|
2020-01-19 20:11:43 +01:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
onkey {
|
|
|
|
|
compatible = "st,stpmic1-onkey";
|
|
|
|
|
interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
|
|
|
|
|
interrupt-names = "onkey-falling", "onkey-rising";
|
|
|
|
|
power-off-time-sec = <10>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
watchdog {
|
|
|
|
|
compatible = "st,stpmic1-wdt";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
touchscreen@49 {
|
|
|
|
|
compatible = "ti,tsc2004";
|
|
|
|
|
reg = <0x49>;
|
|
|
|
|
vio-supply = <&v3v3>;
|
2020-08-28 14:14:12 +02:00
|
|
|
interrupts-extended = <&gpioh 15 IRQ_TYPE_EDGE_FALLING>;
|
2020-01-19 20:11:43 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
eeprom@50 {
|
|
|
|
|
compatible = "atmel,24c02";
|
|
|
|
|
reg = <0x50>;
|
|
|
|
|
pagesize = <16>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&ipcc {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&iwdg2 {
|
|
|
|
|
timeout-sec = <32>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&m4_rproc {
|
|
|
|
|
memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
|
|
|
|
|
<&vdev0vring1>, <&vdev0buffer>;
|
2023-07-11 15:09:07 +02:00
|
|
|
mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
|
|
|
|
|
mbox-names = "vq0", "vq1", "shutdown", "detach";
|
2020-01-19 20:11:43 +01:00
|
|
|
interrupt-parent = <&exti>;
|
|
|
|
|
interrupts = <68 1>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&pwr_regulators {
|
|
|
|
|
vdd-supply = <&vdd>;
|
|
|
|
|
vdd_3v3_usbfs-supply = <&vdd_usb>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&qspi {
|
|
|
|
|
pinctrl-names = "default", "sleep";
|
2022-12-12 09:51:40 +01:00
|
|
|
pinctrl-0 = <&qspi_clk_pins_a
|
|
|
|
|
&qspi_bk1_pins_a
|
|
|
|
|
&qspi_cs1_pins_a>;
|
|
|
|
|
pinctrl-1 = <&qspi_clk_sleep_pins_a
|
|
|
|
|
&qspi_bk1_sleep_pins_a
|
|
|
|
|
&qspi_cs1_sleep_pins_a>;
|
2020-01-19 20:11:43 +01:00
|
|
|
reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
|
2021-06-10 02:25:52 +02:00
|
|
|
flash0: flash@0 {
|
2020-01-19 20:11:43 +01:00
|
|
|
compatible = "jedec,spi-nor";
|
|
|
|
|
reg = <0>;
|
|
|
|
|
spi-rx-bus-width = <4>;
|
|
|
|
|
spi-max-frequency = <108000000>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2022-01-18 21:29:58 +01:00
|
|
|
&rcc {
|
|
|
|
|
/* Connect MCO2 output to ETH_RX_CLK input via pad-pad connection */
|
|
|
|
|
clocks = <&rcc CK_MCO2>;
|
|
|
|
|
clock-names = "ETH_RX_CLK/ETH_REF_CLK";
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Set PLL4P output to 100 MHz to supply SDMMC with faster clock,
|
|
|
|
|
* set MCO2 output to 50 MHz to supply ETHRX clock with PLL4P/2,
|
|
|
|
|
* so that MCO2 behaves as a divider for the ETHRX clock here.
|
|
|
|
|
*/
|
|
|
|
|
assigned-clocks = <&rcc CK_MCO2>, <&rcc PLL4_P>;
|
|
|
|
|
assigned-clock-parents = <&rcc PLL4_P>;
|
|
|
|
|
assigned-clock-rates = <50000000>, <100000000>;
|
|
|
|
|
};
|
|
|
|
|
|
2020-01-19 20:11:43 +01:00
|
|
|
&rng1 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&rtc {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&sdmmc1 {
|
2021-01-24 18:02:58 +01:00
|
|
|
pinctrl-names = "default", "opendrain", "sleep", "init";
|
2020-01-19 20:11:43 +01:00
|
|
|
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
|
|
|
|
|
pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
|
|
|
|
|
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
|
2021-01-24 18:02:58 +01:00
|
|
|
pinctrl-3 = <&sdmmc1_b4_init_pins_a &sdmmc1_dir_init_pins_a>;
|
2020-12-01 12:13:30 +01:00
|
|
|
cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
|
2020-12-01 12:13:31 +01:00
|
|
|
disable-wp;
|
2020-01-19 20:11:43 +01:00
|
|
|
st,sig-dir;
|
|
|
|
|
st,neg-edge;
|
2021-01-24 18:02:58 +01:00
|
|
|
st,use-ckin;
|
|
|
|
|
st,cmd-gpios = <&gpiod 2 0>;
|
|
|
|
|
st,ck-gpios = <&gpioc 12 0>;
|
|
|
|
|
st,ckin-gpios = <&gpioe 4 0>;
|
2020-01-19 20:11:43 +01:00
|
|
|
bus-width = <4>;
|
|
|
|
|
vmmc-supply = <&vdd_sd>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
2020-12-01 12:14:40 +01:00
|
|
|
&sdmmc1_b4_pins_a {
|
|
|
|
|
/*
|
|
|
|
|
* SD bus pull-up resistors:
|
|
|
|
|
* - optional on SoMs with SD voltage translator
|
|
|
|
|
* - mandatory on SoMs without SD voltage translator
|
|
|
|
|
*/
|
|
|
|
|
pins1 {
|
|
|
|
|
bias-pull-up;
|
|
|
|
|
};
|
|
|
|
|
pins2 {
|
|
|
|
|
bias-pull-up;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2020-01-19 20:11:43 +01:00
|
|
|
&sdmmc2 {
|
|
|
|
|
pinctrl-names = "default", "opendrain", "sleep";
|
|
|
|
|
pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
|
|
|
|
|
pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
|
|
|
|
|
pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
|
|
|
|
|
non-removable;
|
|
|
|
|
no-sd;
|
|
|
|
|
no-sdio;
|
|
|
|
|
st,neg-edge;
|
|
|
|
|
bus-width = <8>;
|
|
|
|
|
vmmc-supply = <&v3v3>;
|
|
|
|
|
vqmmc-supply = <&v3v3>;
|
|
|
|
|
mmc-ddr-3_3v;
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&sdmmc3 {
|
|
|
|
|
pinctrl-names = "default", "opendrain", "sleep";
|
|
|
|
|
pinctrl-0 = <&sdmmc3_b4_pins_a>;
|
|
|
|
|
pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
|
|
|
|
|
pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
|
|
|
|
|
broken-cd;
|
|
|
|
|
st,neg-edge;
|
|
|
|
|
bus-width = <4>;
|
|
|
|
|
vmmc-supply = <&v3v3>;
|
|
|
|
|
vqmmc-supply = <&v3v3>;
|
|
|
|
|
mmc-ddr-3_3v;
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&uart4 {
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&uart4_pins_a>;
|
2022-02-03 18:11:13 +01:00
|
|
|
/delete-property/dmas;
|
|
|
|
|
/delete-property/dma-names;
|
2020-01-19 20:11:43 +01:00
|
|
|
status = "okay";
|
|
|
|
|
};
|