ARM: dts: stm32: add STM32MP13 SoCs support
Add initial support of STM32MP13 family. The STM32MP13 SoC diversity is
composed by:
-STM32MP131:
-core: 1*CA7, 17*TIMERS, 5*LPTIMERS, DMA/MDMA/DMAMUX
-storage: 3*SDMCC, 1*QSPI, FMC
-com: USB (OHCI/EHCI, OTG), 5*I2C, 5*SPI/I2S, 8*U(S)ART
-audio: 2*SAI
-network: 1*ETH(GMAC)
-STM32MP133: STM32MP131 + 2*CAN, ETH2(GMAC), ADC1
-STM32MP135: STM32MP133 + DCMIPP, LTDC
A second diversity layer exists for security features:
-STM32MP13xY, "Y" gives information:
-Y = A/D means no cryp IP and no secure boot.
-Y = C/F means cryp IP + secure boot.
This commit adds basic peripheral.
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2021-07-23 15:28:08 +02:00
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
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*/
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#include "stm32mp133.dtsi"
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/ {
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soc {
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2023-11-27 18:08:18 +01:00
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dcmipp: dcmipp@5a000000 {
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compatible = "st,stm32mp13-dcmipp";
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reg = <0x5a000000 0x400>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rcc DCMIPP_R>;
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clocks = <&rcc DCMIPP_K>;
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status = "disabled";
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port {
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};
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};
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ARM: dts: stm32: add LTDC support for STM32MP13x SoC family
STM32MP13x SoC family embeds a new version of LTDC (Liquid crystal
display - Thin film transistor) Display Controller.
It provides a parallel digital RGB (red, green, blue) and signals for
horizontal, vertical synchronization, pixel clock and data enable as
output to interface directly to a variety of LCD-TFT panels.
Main features
* 2 input layers blended together to compose the display
* Cropping of layers from any input size and location
* Multiple input pixel formats:
– Predefined ARGB, with 7 formats: ARGB8888, ABGR8888, RGBA8888,
BGRA8888, RGB565, BGR565, RGB888packed.
– Flexible ARGB, allowing any width and location for A,R,G,B
components.
– Predefined YUV, with 3 formats: YUV422-1L (FourCC: YUYV,
Interleaved), YUV420-2L (FourCC: NV12, semi planar), YUV420-3L
(FourCC: Yxx, full planar) with some flexibility on the sequence of
the component.
* Color look-up table (CLUT) up to 256 colors (256x24 bits) per layer
* Color transparency keying
* Composition with flexible window position and size versus output
display
* Blending with flexible layer order and alpha value (per pixel or
constant)
* Background underlying color
* Gamma with non-linear configurable table
* Dithering for output with less bits per component (pseudo-random on
2 bits)
* Polarity inversion for HSync, VSync, and DataEnable outputs
* Output as RGB888 24 bpp or YUV422 16 bpp
* Secure layer (using Layer2) capability, with grouped regs and
additional interrupt set
* Interrupts based on 7 different events
* AXI master interface with long efficient bursts (64 or 128 bytes)
Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
Signed-off-by: Yannick Fertre <yannick.fertre@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2024-02-23 13:36:48 +01:00
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ltdc: display-controller@5a001000 {
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compatible = "st,stm32-ltdc";
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reg = <0x5a001000 0x400>;
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interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc LTDC_PX>;
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clock-names = "lcd";
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resets = <&scmi_reset RST_SCMI_LTDC>;
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status = "disabled";
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};
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ARM: dts: stm32: add STM32MP13 SoCs support
Add initial support of STM32MP13 family. The STM32MP13 SoC diversity is
composed by:
-STM32MP131:
-core: 1*CA7, 17*TIMERS, 5*LPTIMERS, DMA/MDMA/DMAMUX
-storage: 3*SDMCC, 1*QSPI, FMC
-com: USB (OHCI/EHCI, OTG), 5*I2C, 5*SPI/I2S, 8*U(S)ART
-audio: 2*SAI
-network: 1*ETH(GMAC)
-STM32MP133: STM32MP131 + 2*CAN, ETH2(GMAC), ADC1
-STM32MP135: STM32MP133 + DCMIPP, LTDC
A second diversity layer exists for security features:
-STM32MP13xY, "Y" gives information:
-Y = A/D means no cryp IP and no secure boot.
-Y = C/F means cryp IP + secure boot.
This commit adds basic peripheral.
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2021-07-23 15:28:08 +02:00
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};
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};
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