2020-06-29 05:54:52 +03:00
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// SPDX-License-Identifier: GPL-2.0
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#include <dt-bindings/input/gpio-keys.h>
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#include <dt-bindings/input/input.h>
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2020-08-14 00:34:09 +03:00
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#include <dt-bindings/power/summit,smb347-charger.h>
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2020-06-29 05:54:52 +03:00
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#include <dt-bindings/thermal/thermal.h>
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#include "tegra30.dtsi"
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#include "tegra30-cpu-opp.dtsi"
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#include "tegra30-cpu-opp-microvolt.dtsi"
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2021-12-12 00:14:06 +03:00
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#include "tegra30-asus-lvds-display.dtsi"
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2020-06-29 05:54:52 +03:00
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/ {
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aliases {
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2020-09-06 22:00:06 +03:00
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mmc0 = &sdmmc4; /* eMMC */
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mmc1 = &sdmmc3; /* WiFi */
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2020-06-29 05:54:52 +03:00
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rtc0 = &pmic;
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rtc1 = "/rtc@7000e000";
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serial1 = &uartc; /* Bluetooth */
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serial2 = &uartb; /* GPS */
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};
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/*
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* The decompressor and also some bootloaders rely on a
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* pre-existing /chosen node to be available to insert the
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* command line and merge other ATAGS info.
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*/
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chosen {};
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ARM: tegra: Sort nodes by unit-address, then alphabetically
Nodes in device tree should be sorted by unit-address, followed by nodes
without a unit-address, sorted alphabetically. Some exceptions are the
top-level aliases, chosen, firmware, memory and reserved-memory nodes,
which are expected to come first.
These rules apply recursively with some exceptions, such as pinmux nodes
or regulator nodes, which often follow more complicated ordering (often
by "importance").
While at it, change the name of some of the nodes to follow standard
naming conventions, which helps with the sorting order and reduces the
amount of warnings from the DT validation tools.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-22 11:21:18 +01:00
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firmware {
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trusted-foundations {
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compatible = "tlm,trusted-foundations";
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tlm,version-major = <0x0>;
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tlm,version-minor = <0x0>;
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};
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};
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2020-06-29 05:54:52 +03:00
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memory@80000000 {
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reg = <0x80000000 0x40000000>;
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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linux,cma@80000000 {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x80000000 0x30000000>;
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size = <0x10000000>; /* 256MiB */
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linux,cma-default;
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reusable;
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};
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ramoops@bfdf0000 {
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compatible = "ramoops";
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reg = <0xbfdf0000 0x10000>; /* 64kB */
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console-size = <0x8000>; /* 32kB */
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record-size = <0x400>; /* 1kB */
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ecc-size = <16>;
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};
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trustzone@bfe00000 {
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reg = <0xbfe00000 0x200000>;
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no-map;
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};
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};
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gpio@6000d000 {
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ARM: tegra: Sort nodes by unit-address, then alphabetically
Nodes in device tree should be sorted by unit-address, followed by nodes
without a unit-address, sorted alphabetically. Some exceptions are the
top-level aliases, chosen, firmware, memory and reserved-memory nodes,
which are expected to come first.
These rules apply recursively with some exceptions, such as pinmux nodes
or regulator nodes, which often follow more complicated ordering (often
by "importance").
While at it, change the name of some of the nodes to follow standard
naming conventions, which helps with the sorting order and reduces the
amount of warnings from the DT validation tools.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-22 11:21:18 +01:00
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init-low-power-mode-hog {
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gpio-hog;
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gpios = <TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
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input;
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};
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2020-11-04 17:12:49 +03:00
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init-mode-hog {
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2020-06-29 05:54:52 +03:00
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gpio-hog;
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2022-05-26 22:35:16 +02:00
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gpios = <TEGRA_GPIO(DD, 7) GPIO_ACTIVE_HIGH>,
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2020-06-29 05:54:52 +03:00
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<TEGRA_GPIO(CC, 6) GPIO_ACTIVE_HIGH>,
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<TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
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output-low;
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};
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};
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pinmux@70000868 {
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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state_default: pinmux {
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clk_32k_out_pa0 {
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nvidia,pins = "clk_32k_out_pa0";
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nvidia,function = "blink";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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uart3_cts_n_pa1 {
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nvidia,pins = "uart3_cts_n_pa1",
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"uart3_rxd_pw7";
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nvidia,function = "uartc";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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dap2_fs_pa2 {
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nvidia,pins = "dap2_fs_pa2",
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"dap2_sclk_pa3",
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"dap2_din_pa4",
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"dap2_dout_pa5";
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nvidia,function = "i2s1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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sdmmc3_clk_pa6 {
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nvidia,pins = "sdmmc3_clk_pa6";
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nvidia,function = "sdmmc3";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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sdmmc3_cmd_pa7 {
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nvidia,pins = "sdmmc3_cmd_pa7",
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"sdmmc3_dat3_pb4",
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"sdmmc3_dat2_pb5",
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"sdmmc3_dat1_pb6",
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"sdmmc3_dat0_pb7",
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"sdmmc3_dat4_pd1",
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"sdmmc3_dat6_pd3",
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"sdmmc3_dat7_pd4";
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nvidia,function = "sdmmc3";
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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gmi_a17_pb0 {
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nvidia,pins = "gmi_a17_pb0",
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"gmi_a18_pb1";
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nvidia,function = "uartd";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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lcd_pwr0_pb2 {
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nvidia,pins = "lcd_pwr0_pb2",
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"lcd_pwr1_pc1",
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"lcd_m1_pw1";
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nvidia,function = "displaya";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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lcd_pclk_pb3 {
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nvidia,pins = "lcd_pclk_pb3",
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"lcd_d0_pe0",
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"lcd_d1_pe1",
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"lcd_d2_pe2",
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"lcd_d3_pe3",
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"lcd_d4_pe4",
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"lcd_d5_pe5",
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"lcd_d6_pe6",
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"lcd_d7_pe7",
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"lcd_d8_pf0",
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"lcd_d9_pf1",
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"lcd_d10_pf2",
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"lcd_d11_pf3",
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"lcd_d12_pf4",
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"lcd_d13_pf5",
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"lcd_d14_pf6",
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"lcd_d15_pf7",
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"lcd_de_pj1",
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"lcd_hsync_pj3",
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"lcd_vsync_pj4",
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"lcd_d16_pm0",
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"lcd_d17_pm1",
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"lcd_d18_pm2",
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"lcd_d19_pm3",
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"lcd_d20_pm4",
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"lcd_d21_pm5",
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"lcd_d22_pm6",
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"lcd_d23_pm7",
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"lcd_cs0_n_pn4",
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"lcd_sdout_pn5",
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"lcd_dc0_pn6",
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"lcd_cs1_n_pw0",
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"lcd_sdin_pz2",
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"lcd_sck_pz4";
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nvidia,function = "displaya";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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uart3_rts_n_pc0 {
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nvidia,pins = "uart3_rts_n_pc0",
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"uart3_txd_pw6";
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nvidia,function = "uartc";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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uart2_txd_pc2 {
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nvidia,pins = "uart2_txd_pc2",
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"uart2_rts_n_pj6";
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nvidia,function = "uartb";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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uart2_rxd_pc3 {
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nvidia,pins = "uart2_rxd_pc3",
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"uart2_cts_n_pj5";
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nvidia,function = "uartb";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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gen1_i2c_scl_pc4 {
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nvidia,pins = "gen1_i2c_scl_pc4",
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"gen1_i2c_sda_pc5";
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nvidia,function = "i2c1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,open-drain = <TEGRA_PIN_ENABLE>;
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};
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gmi_wp_n_pc7 {
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nvidia,pins = "gmi_wp_n_pc7",
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"gmi_wait_pi7",
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"gmi_cs4_n_pk2",
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"gmi_cs3_n_pk4";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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gmi_ad12_ph4 {
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nvidia,pins = "gmi_ad12_ph4",
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"gmi_cs0_n_pj0",
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"gmi_cs1_n_pj2",
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"gmi_cs2_n_pk3";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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sdmmc3_dat5_pd0 {
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nvidia,pins = "sdmmc3_dat5_pd0";
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nvidia,function = "sdmmc3";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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gmi_ad0_pg0 {
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nvidia,pins = "gmi_ad0_pg0",
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"gmi_ad1_pg1",
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"gmi_ad14_ph6",
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"pu1";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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gmi_ad2_pg2 {
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nvidia,pins = "gmi_ad2_pg2",
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"gmi_ad3_pg3",
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"gmi_ad6_pg6",
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"gmi_ad7_pg7";
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nvidia,function = "rsvd1";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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gmi_ad4_pg4 {
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nvidia,pins = "gmi_ad4_pg4",
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"gmi_ad5_pg5";
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nvidia,function = "nand";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
gmi_ad8_ph0 {
|
|
|
|
|
nvidia,pins = "gmi_ad8_ph0";
|
|
|
|
|
nvidia,function = "pwm0";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
gmi_ad9_ph1 {
|
|
|
|
|
nvidia,pins = "gmi_ad9_ph1";
|
|
|
|
|
nvidia,function = "rsvd4";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
gmi_ad10_ph2 {
|
|
|
|
|
nvidia,pins = "gmi_ad10_ph2";
|
|
|
|
|
nvidia,function = "pwm2";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
gmi_ad11_ph3 {
|
|
|
|
|
nvidia,pins = "gmi_ad11_ph3";
|
|
|
|
|
nvidia,function = "pwm3";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
gmi_ad13_ph5 {
|
|
|
|
|
nvidia,pins = "gmi_ad13_ph5",
|
|
|
|
|
"gmi_wr_n_pi0",
|
|
|
|
|
"gmi_oe_n_pi1",
|
|
|
|
|
"gmi_adv_n_pk0";
|
|
|
|
|
nvidia,function = "rsvd1";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
gmi_ad15_ph7 {
|
|
|
|
|
nvidia,pins = "gmi_ad15_ph7";
|
|
|
|
|
nvidia,function = "rsvd1";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
gmi_dqs_pi2 {
|
|
|
|
|
nvidia,pins = "gmi_dqs_pi2",
|
|
|
|
|
"pu2",
|
|
|
|
|
"pv1";
|
|
|
|
|
nvidia,function = "rsvd1";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
gmi_rst_n_pi4 {
|
|
|
|
|
nvidia,pins = "gmi_rst_n_pi4";
|
|
|
|
|
nvidia,function = "nand";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
gmi_iordy_pi5 {
|
|
|
|
|
nvidia,pins = "gmi_iordy_pi5";
|
|
|
|
|
nvidia,function = "rsvd1";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
gmi_cs7_n_pi6 {
|
|
|
|
|
nvidia,pins = "gmi_cs7_n_pi6",
|
|
|
|
|
"gmi_clk_pk1";
|
|
|
|
|
nvidia,function = "nand";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
gmi_a16_pj7 {
|
|
|
|
|
nvidia,pins = "gmi_a16_pj7",
|
|
|
|
|
"gmi_a19_pk7";
|
|
|
|
|
nvidia,function = "uartd";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
spdif_out_pk5 {
|
|
|
|
|
nvidia,pins = "spdif_out_pk5";
|
|
|
|
|
nvidia,function = "spdif";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
spdif_in_pk6 {
|
|
|
|
|
nvidia,pins = "spdif_in_pk6";
|
|
|
|
|
nvidia,function = "spdif";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
dap1_fs_pn0 {
|
|
|
|
|
nvidia,pins = "dap1_fs_pn0",
|
|
|
|
|
"dap1_din_pn1",
|
|
|
|
|
"dap1_dout_pn2",
|
|
|
|
|
"dap1_sclk_pn3";
|
|
|
|
|
nvidia,function = "i2s0";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
hdmi_int_pn7 {
|
|
|
|
|
nvidia,pins = "hdmi_int_pn7";
|
|
|
|
|
nvidia,function = "hdmi";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
ulpi_data7_po0 {
|
|
|
|
|
nvidia,pins = "ulpi_data7_po0";
|
|
|
|
|
nvidia,function = "uarta";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
ulpi_data3_po4 {
|
|
|
|
|
nvidia,pins = "ulpi_data3_po4";
|
|
|
|
|
nvidia,function = "ulpi";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
dap3_fs_pp0 {
|
|
|
|
|
nvidia,pins = "dap3_fs_pp0";
|
|
|
|
|
nvidia,function = "i2s2";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
dap4_fs_pp4 {
|
|
|
|
|
nvidia,pins = "dap4_fs_pp4",
|
|
|
|
|
"dap4_din_pp5",
|
|
|
|
|
"dap4_dout_pp6",
|
|
|
|
|
"dap4_sclk_pp7";
|
|
|
|
|
nvidia,function = "i2s3";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
kb_col0_pq0 {
|
|
|
|
|
nvidia,pins = "kb_col0_pq0",
|
|
|
|
|
"kb_col1_pq1",
|
|
|
|
|
"kb_row1_pr1";
|
|
|
|
|
nvidia,function = "kbc";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
kb_col2_pq2 {
|
|
|
|
|
nvidia,pins = "kb_col2_pq2",
|
|
|
|
|
"kb_col3_pq3";
|
|
|
|
|
nvidia,function = "rsvd4";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
kb_col4_pq4 {
|
|
|
|
|
nvidia,pins = "kb_col4_pq4",
|
|
|
|
|
"kb_col5_pq5",
|
|
|
|
|
"kb_col7_pq7",
|
|
|
|
|
"kb_row2_pr2",
|
|
|
|
|
"kb_row4_pr4",
|
|
|
|
|
"kb_row5_pr5",
|
|
|
|
|
"kb_row14_ps6";
|
|
|
|
|
nvidia,function = "kbc";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
kb_row0_pr0 {
|
|
|
|
|
nvidia,pins = "kb_row0_pr0";
|
|
|
|
|
nvidia,function = "rsvd4";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
kb_row6_pr6 {
|
|
|
|
|
nvidia,pins = "kb_row6_pr6",
|
|
|
|
|
"kb_row8_ps0",
|
|
|
|
|
"kb_row9_ps1",
|
|
|
|
|
"kb_row10_ps2";
|
|
|
|
|
nvidia,function = "kbc";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
kb_row11_ps3 {
|
|
|
|
|
nvidia,pins = "kb_row11_ps3",
|
|
|
|
|
"kb_row12_ps4";
|
|
|
|
|
nvidia,function = "kbc";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
gen2_i2c_scl_pt5 {
|
|
|
|
|
nvidia,pins = "gen2_i2c_scl_pt5",
|
|
|
|
|
"gen2_i2c_sda_pt6";
|
|
|
|
|
nvidia,function = "i2c2";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
sdmmc4_cmd_pt7 {
|
|
|
|
|
nvidia,pins = "sdmmc4_cmd_pt7",
|
|
|
|
|
"sdmmc4_dat0_paa0",
|
|
|
|
|
"sdmmc4_dat1_paa1",
|
|
|
|
|
"sdmmc4_dat2_paa2",
|
|
|
|
|
"sdmmc4_dat3_paa3",
|
|
|
|
|
"sdmmc4_dat4_paa4",
|
|
|
|
|
"sdmmc4_dat5_paa5",
|
|
|
|
|
"sdmmc4_dat6_paa6",
|
|
|
|
|
"sdmmc4_dat7_paa7";
|
|
|
|
|
nvidia,function = "sdmmc4";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
pu0 {
|
|
|
|
|
nvidia,pins = "pu0",
|
|
|
|
|
"pu6";
|
|
|
|
|
nvidia,function = "rsvd4";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
jtag_rtck_pu7 {
|
|
|
|
|
nvidia,pins = "jtag_rtck_pu7";
|
|
|
|
|
nvidia,function = "rtck";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
pv0 {
|
|
|
|
|
nvidia,pins = "pv0";
|
|
|
|
|
nvidia,function = "rsvd1";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
ddc_scl_pv4 {
|
|
|
|
|
nvidia,pins = "ddc_scl_pv4",
|
|
|
|
|
"ddc_sda_pv5";
|
|
|
|
|
nvidia,function = "i2c4";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
crt_hsync_pv6 {
|
|
|
|
|
nvidia,pins = "crt_hsync_pv6",
|
|
|
|
|
"crt_vsync_pv7";
|
|
|
|
|
nvidia,function = "crt";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
spi2_cs1_n_pw2 {
|
|
|
|
|
nvidia,pins = "spi2_cs1_n_pw2",
|
|
|
|
|
"spi2_miso_px1",
|
|
|
|
|
"spi2_sck_px2";
|
|
|
|
|
nvidia,function = "spi2";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
clk1_out_pw4 {
|
|
|
|
|
nvidia,pins = "clk1_out_pw4";
|
|
|
|
|
nvidia,function = "extperiph1";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
clk2_out_pw5 {
|
|
|
|
|
nvidia,pins = "clk2_out_pw5";
|
|
|
|
|
nvidia,function = "extperiph2";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
spi2_cs0_n_px3 {
|
|
|
|
|
nvidia,pins = "spi2_cs0_n_px3";
|
|
|
|
|
nvidia,function = "spi6";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
spi1_mosi_px4 {
|
|
|
|
|
nvidia,pins = "spi1_mosi_px4",
|
|
|
|
|
"spi1_cs0_n_px6";
|
|
|
|
|
nvidia,function = "spi1";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
ulpi_clk_py0 {
|
|
|
|
|
nvidia,pins = "ulpi_clk_py0",
|
|
|
|
|
"ulpi_dir_py1";
|
|
|
|
|
nvidia,function = "ulpi";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
sdmmc1_dat3_py4 {
|
|
|
|
|
nvidia,pins = "sdmmc1_dat3_py4",
|
|
|
|
|
"sdmmc1_dat2_py5",
|
|
|
|
|
"sdmmc1_dat1_py6",
|
|
|
|
|
"sdmmc1_dat0_py7",
|
|
|
|
|
"sdmmc1_cmd_pz1";
|
|
|
|
|
nvidia,function = "sdmmc1";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
sdmmc1_clk_pz0 {
|
|
|
|
|
nvidia,pins = "sdmmc1_clk_pz0";
|
|
|
|
|
nvidia,function = "sdmmc1";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
lcd_wr_n_pz3 {
|
|
|
|
|
nvidia,pins = "lcd_wr_n_pz3";
|
|
|
|
|
nvidia,function = "displaya";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
sys_clk_req_pz5 {
|
|
|
|
|
nvidia,pins = "sys_clk_req_pz5";
|
|
|
|
|
nvidia,function = "sysclk";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
pwr_i2c_scl_pz6 {
|
|
|
|
|
nvidia,pins = "pwr_i2c_scl_pz6",
|
|
|
|
|
"pwr_i2c_sda_pz7";
|
|
|
|
|
nvidia,function = "i2cpwr";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
pbb0 {
|
|
|
|
|
nvidia,pins = "pbb0",
|
|
|
|
|
"pcc1";
|
|
|
|
|
nvidia,function = "rsvd2";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
cam_i2c_scl_pbb1 {
|
|
|
|
|
nvidia,pins = "cam_i2c_scl_pbb1",
|
|
|
|
|
"cam_i2c_sda_pbb2";
|
|
|
|
|
nvidia,function = "i2c3";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
pbb3 {
|
|
|
|
|
nvidia,pins = "pbb3";
|
|
|
|
|
nvidia,function = "vgp3";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
pbb4 {
|
|
|
|
|
nvidia,pins = "pbb4";
|
|
|
|
|
nvidia,function = "vgp4";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
pbb5 {
|
|
|
|
|
nvidia,pins = "pbb5";
|
|
|
|
|
nvidia,function = "vgp5";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
pbb6 {
|
|
|
|
|
nvidia,pins = "pbb6";
|
|
|
|
|
nvidia,function = "vgp6";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
pbb7 {
|
|
|
|
|
nvidia,pins = "pbb7",
|
|
|
|
|
"pcc2";
|
|
|
|
|
nvidia,function = "i2s4";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
cam_mclk_pcc0 {
|
|
|
|
|
nvidia,pins = "cam_mclk_pcc0";
|
|
|
|
|
nvidia,function = "vi_alt3";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
sdmmc4_rst_n_pcc3 {
|
|
|
|
|
nvidia,pins = "sdmmc4_rst_n_pcc3";
|
|
|
|
|
nvidia,function = "rsvd2";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
sdmmc4_clk_pcc4 {
|
|
|
|
|
nvidia,pins = "sdmmc4_clk_pcc4";
|
|
|
|
|
nvidia,function = "sdmmc4";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
clk2_req_pcc5 {
|
|
|
|
|
nvidia,pins = "clk2_req_pcc5";
|
|
|
|
|
nvidia,function = "dap";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
pex_l2_rst_n_pcc6 {
|
|
|
|
|
nvidia,pins = "pex_l2_rst_n_pcc6",
|
|
|
|
|
"pex_l2_clkreq_n_pcc7";
|
|
|
|
|
nvidia,function = "pcie";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
pex_wake_n_pdd3 {
|
|
|
|
|
nvidia,pins = "pex_wake_n_pdd3",
|
|
|
|
|
"pex_l2_prsnt_n_pdd7";
|
|
|
|
|
nvidia,function = "pcie";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
clk3_out_pee0 {
|
|
|
|
|
nvidia,pins = "clk3_out_pee0";
|
|
|
|
|
nvidia,function = "extperiph3";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
clk1_req_pee2 {
|
|
|
|
|
nvidia,pins = "clk1_req_pee2";
|
|
|
|
|
nvidia,function = "dap";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
hdmi_cec_pee3 {
|
|
|
|
|
nvidia,pins = "hdmi_cec_pee3";
|
|
|
|
|
nvidia,function = "cec";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
owr {
|
|
|
|
|
nvidia,pins = "owr";
|
|
|
|
|
nvidia,function = "owr";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
drive_dap1 {
|
|
|
|
|
nvidia,pins = "drive_dap1",
|
|
|
|
|
"drive_dap2",
|
|
|
|
|
"drive_dbg",
|
|
|
|
|
"drive_at5",
|
|
|
|
|
"drive_gme",
|
|
|
|
|
"drive_ddc",
|
|
|
|
|
"drive_ao1",
|
|
|
|
|
"drive_uart3";
|
|
|
|
|
nvidia,high-speed-mode = <0>;
|
|
|
|
|
nvidia,schmitt = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
|
|
|
|
|
nvidia,pull-down-strength = <31>;
|
|
|
|
|
nvidia,pull-up-strength = <31>;
|
|
|
|
|
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
|
|
|
|
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
|
|
|
|
};
|
|
|
|
|
drive_sdio1 {
|
|
|
|
|
nvidia,pins = "drive_sdio1",
|
|
|
|
|
"drive_sdio3";
|
|
|
|
|
nvidia,high-speed-mode = <0>;
|
|
|
|
|
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,pull-down-strength = <46>;
|
|
|
|
|
nvidia,pull-up-strength = <42>;
|
|
|
|
|
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
|
|
|
|
|
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
|
|
|
|
|
};
|
|
|
|
|
drive_gma {
|
|
|
|
|
nvidia,pins = "drive_gma",
|
|
|
|
|
"drive_gmb",
|
|
|
|
|
"drive_gmc",
|
|
|
|
|
"drive_gmd";
|
|
|
|
|
nvidia,pull-down-strength = <9>;
|
|
|
|
|
nvidia,pull-up-strength = <9>;
|
|
|
|
|
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
|
|
|
|
|
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uartb: serial@70006040 {
|
|
|
|
|
compatible = "nvidia,tegra30-hsuart";
|
2023-07-17 18:33:29 +02:00
|
|
|
reset-names = "serial";
|
2021-12-07 11:11:33 +01:00
|
|
|
/delete-property/ reg-shift;
|
2020-06-29 05:54:52 +03:00
|
|
|
/* GPS BCM4751 */
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uartc: serial@70006200 {
|
|
|
|
|
compatible = "nvidia,tegra30-hsuart";
|
2023-07-17 18:33:29 +02:00
|
|
|
reset-names = "serial";
|
2021-12-07 11:11:33 +01:00
|
|
|
/delete-property/ reg-shift;
|
2020-06-29 05:54:52 +03:00
|
|
|
status = "okay";
|
|
|
|
|
|
|
|
|
|
nvidia,adjust-baud-rates = <0 9600 100>,
|
|
|
|
|
<9600 115200 200>,
|
|
|
|
|
<1000000 4000000 136>;
|
|
|
|
|
|
|
|
|
|
/* Azurewave AW-NH665 BCM4330B1 */
|
|
|
|
|
bluetooth {
|
|
|
|
|
compatible = "brcm,bcm4330-bt";
|
|
|
|
|
|
2021-09-27 02:37:04 +03:00
|
|
|
interrupt-parent = <&gpio>;
|
|
|
|
|
interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>;
|
|
|
|
|
interrupt-names = "host-wakeup";
|
|
|
|
|
|
2020-06-29 05:54:52 +03:00
|
|
|
max-speed = <4000000>;
|
|
|
|
|
|
|
|
|
|
clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
|
|
|
|
|
clock-names = "txco";
|
|
|
|
|
|
|
|
|
|
vbat-supply = <&vdd_3v3_sys>;
|
|
|
|
|
vddio-supply = <&vdd_1v8>;
|
|
|
|
|
|
|
|
|
|
device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
|
2022-05-26 22:35:16 +02:00
|
|
|
shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
|
2020-06-29 05:54:52 +03:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pwm: pwm@7000a000 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c@7000c400 {
|
|
|
|
|
clock-frequency = <400000>;
|
|
|
|
|
status = "okay";
|
2020-08-14 03:21:38 +03:00
|
|
|
|
|
|
|
|
touchscreen@10 {
|
2022-05-26 22:35:16 +02:00
|
|
|
compatible = "elan,ektf3624";
|
2020-08-14 03:21:38 +03:00
|
|
|
reg = <0x10>;
|
|
|
|
|
|
|
|
|
|
interrupt-parent = <&gpio>;
|
|
|
|
|
interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_LEVEL_LOW>;
|
|
|
|
|
|
|
|
|
|
reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>;
|
|
|
|
|
|
|
|
|
|
vcc33-supply = <&vcc_3v3_ts>;
|
|
|
|
|
vccio-supply = <&vcc_3v3_ts>;
|
|
|
|
|
|
|
|
|
|
touchscreen-size-x = <2112>;
|
|
|
|
|
touchscreen-size-y = <1280>;
|
|
|
|
|
touchscreen-swapped-x-y;
|
|
|
|
|
touchscreen-inverted-x;
|
|
|
|
|
};
|
2020-06-29 05:54:52 +03:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c@7000c500 {
|
|
|
|
|
clock-frequency = <100000>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
|
|
|
|
|
compass@e {
|
|
|
|
|
compatible = "asahi-kasei,ak8974";
|
|
|
|
|
reg = <0x0e>;
|
|
|
|
|
|
|
|
|
|
interrupt-parent = <&gpio>;
|
|
|
|
|
interrupts = <TEGRA_GPIO(W, 0) IRQ_TYPE_EDGE_RISING>;
|
|
|
|
|
|
|
|
|
|
avdd-supply = <&vdd_3v3_sys>;
|
|
|
|
|
dvdd-supply = <&vdd_1v8>;
|
|
|
|
|
|
|
|
|
|
mount-matrix = "0", "-1", "0",
|
|
|
|
|
"-1", "0", "0",
|
|
|
|
|
"0", "0", "-1";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
light-sensor@1c {
|
|
|
|
|
compatible = "dynaimage,al3010";
|
|
|
|
|
reg = <0x1c>;
|
|
|
|
|
|
|
|
|
|
interrupt-parent = <&gpio>;
|
|
|
|
|
interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
|
|
|
|
|
vdd-supply = <&vdd_3v3_sys>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
accelerometer@68 {
|
|
|
|
|
compatible = "invensense,mpu6050";
|
|
|
|
|
reg = <0x68>;
|
|
|
|
|
|
|
|
|
|
interrupt-parent = <&gpio>;
|
|
|
|
|
interrupts = <TEGRA_GPIO(X, 1) IRQ_TYPE_EDGE_RISING>;
|
|
|
|
|
|
|
|
|
|
vdd-supply = <&vdd_3v3_sys>;
|
|
|
|
|
vddio-supply = <&vdd_1v8>;
|
|
|
|
|
|
|
|
|
|
mount-matrix = "0", "-1", "0",
|
|
|
|
|
"-1", "0", "0",
|
|
|
|
|
"0", "0", "-1";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c@7000d000 {
|
|
|
|
|
clock-frequency = <100000>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
|
|
|
|
|
rt5640: audio-codec@1c {
|
|
|
|
|
compatible = "realtek,rt5640";
|
|
|
|
|
reg = <0x1c>;
|
|
|
|
|
|
|
|
|
|
realtek,dmic1-data-pin = <1>;
|
2024-01-29 20:10:49 +02:00
|
|
|
|
|
|
|
|
clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
|
|
|
|
|
clock-names = "mclk";
|
2020-06-29 05:54:52 +03:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
nct72: temperature-sensor@4c {
|
|
|
|
|
compatible = "onnn,nct1008";
|
|
|
|
|
reg = <0x4c>;
|
|
|
|
|
vcc-supply = <&vdd_3v3_sys>;
|
2021-08-03 00:19:36 +03:00
|
|
|
|
|
|
|
|
interrupt-parent = <&gpio>;
|
|
|
|
|
interrupts = <TEGRA_GPIO(S, 3) IRQ_TYPE_EDGE_FALLING>;
|
|
|
|
|
|
2020-06-29 05:54:52 +03:00
|
|
|
#thermal-sensor-cells = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
2020-08-14 00:34:09 +03:00
|
|
|
fuel-gauge@55 {
|
2020-06-29 05:54:52 +03:00
|
|
|
compatible = "ti,bq27541";
|
|
|
|
|
reg = <0x55>;
|
2020-08-14 00:34:09 +03:00
|
|
|
power-supplies = <&power_supply>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
power_supply: charger@6a {
|
|
|
|
|
compatible = "summit,smb347";
|
|
|
|
|
reg = <0x6a>;
|
|
|
|
|
|
|
|
|
|
interrupt-parent = <&gpio>;
|
|
|
|
|
interrupts = <TEGRA_GPIO(V, 1) IRQ_TYPE_EDGE_BOTH>;
|
|
|
|
|
|
|
|
|
|
summit,enable-charge-control = <SMB3XX_CHG_ENABLE_PIN_ACTIVE_LOW>;
|
2021-09-12 21:17:17 +03:00
|
|
|
summit,inok-polarity = <SMB3XX_SYSOK_INOK_ACTIVE_LOW>;
|
2020-08-14 00:34:09 +03:00
|
|
|
summit,enable-usb-charging;
|
|
|
|
|
|
|
|
|
|
monitored-battery = <&battery_cell>;
|
2021-09-12 21:17:17 +03:00
|
|
|
|
|
|
|
|
usb_vbus: usb-vbus {
|
|
|
|
|
regulator-name = "usb_vbus";
|
|
|
|
|
regulator-min-microvolt = <5000000>;
|
|
|
|
|
regulator-max-microvolt = <5000000>;
|
|
|
|
|
regulator-min-microamp = <750000>;
|
|
|
|
|
regulator-max-microamp = <750000>;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* SMB347 INOK input pin is connected to PMIC's
|
|
|
|
|
* ACOK output, which is fixed to ACTIVE_LOW as
|
|
|
|
|
* long as battery voltage is in a good range.
|
|
|
|
|
*
|
|
|
|
|
* Active INOK disables SMB347 output, so polarity
|
|
|
|
|
* needs to be toggled when we want to get the
|
|
|
|
|
* output.
|
|
|
|
|
*/
|
|
|
|
|
summit,needs-inok-toggle;
|
|
|
|
|
};
|
2020-06-29 05:54:52 +03:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pmc@7000e400 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
nvidia,invert-interrupt;
|
|
|
|
|
nvidia,suspend-mode = <1>;
|
|
|
|
|
nvidia,cpu-pwr-good-time = <2000>;
|
|
|
|
|
nvidia,cpu-pwr-off-time = <200>;
|
|
|
|
|
nvidia,core-pwr-good-time = <3845 3845>;
|
|
|
|
|
nvidia,core-pwr-off-time = <0>;
|
|
|
|
|
nvidia,core-power-req-active-high;
|
|
|
|
|
nvidia,sys-clock-req-active-high;
|
2021-12-01 02:23:44 +03:00
|
|
|
core-supply = <&vdd_core>;
|
2020-06-29 05:54:52 +03:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ahub@70080000 {
|
|
|
|
|
i2s@70080400 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2020-09-06 22:00:06 +03:00
|
|
|
sdmmc3: mmc@78000400 {
|
2020-06-29 05:54:52 +03:00
|
|
|
status = "okay";
|
|
|
|
|
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
2020-08-23 17:47:25 +03:00
|
|
|
assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
|
|
|
|
|
assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>;
|
|
|
|
|
assigned-clock-rates = <50000000>;
|
|
|
|
|
|
|
|
|
|
max-frequency = <50000000>;
|
2020-06-29 05:54:52 +03:00
|
|
|
keep-power-in-suspend;
|
|
|
|
|
bus-width = <4>;
|
|
|
|
|
non-removable;
|
|
|
|
|
|
|
|
|
|
mmc-pwrseq = <&brcm_wifi_pwrseq>;
|
|
|
|
|
vmmc-supply = <&vdd_3v3_sys>;
|
|
|
|
|
vqmmc-supply = <&vdd_1v8>;
|
|
|
|
|
|
|
|
|
|
/* Azurewave AW-NH665 BCM4330 */
|
|
|
|
|
wifi@1 {
|
|
|
|
|
reg = <1>;
|
|
|
|
|
compatible = "brcm,bcm4329-fmac";
|
|
|
|
|
interrupt-parent = <&gpio>;
|
|
|
|
|
interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
interrupt-names = "host-wake";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2020-09-06 22:00:06 +03:00
|
|
|
sdmmc4: mmc@78000600 {
|
2020-06-29 05:54:52 +03:00
|
|
|
status = "okay";
|
|
|
|
|
bus-width = <8>;
|
|
|
|
|
vmmc-supply = <&vcore_emmc>;
|
|
|
|
|
vqmmc-supply = <&vdd_1v8>;
|
|
|
|
|
non-removable;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb@7d000000 {
|
|
|
|
|
compatible = "nvidia,tegra30-udc";
|
|
|
|
|
status = "okay";
|
2021-09-12 21:17:17 +03:00
|
|
|
dr_mode = "otg";
|
|
|
|
|
vbus-supply = <&usb_vbus>;
|
2020-06-29 05:54:52 +03:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb-phy@7d000000 {
|
|
|
|
|
status = "okay";
|
2021-09-12 21:17:17 +03:00
|
|
|
dr_mode = "otg";
|
2020-06-29 05:54:52 +03:00
|
|
|
nvidia,hssync-start-delay = <0>;
|
|
|
|
|
nvidia,xcvr-lsfslew = <2>;
|
|
|
|
|
nvidia,xcvr-lsrslew = <2>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
backlight: backlight {
|
|
|
|
|
compatible = "pwm-backlight";
|
|
|
|
|
|
|
|
|
|
power-supply = <&vdd_5v0_sys>;
|
|
|
|
|
pwms = <&pwm 0 50000>;
|
|
|
|
|
|
|
|
|
|
brightness-levels = <1 255>;
|
|
|
|
|
num-interpolated-steps = <254>;
|
|
|
|
|
default-brightness-level = <15>;
|
|
|
|
|
};
|
|
|
|
|
|
2020-08-14 00:34:09 +03:00
|
|
|
battery_cell: battery-cell {
|
|
|
|
|
compatible = "simple-battery";
|
|
|
|
|
constant-charge-current-max-microamp = <1800000>;
|
|
|
|
|
operating-range-celsius = <0 45>;
|
|
|
|
|
};
|
|
|
|
|
|
2020-06-29 05:54:52 +03:00
|
|
|
/* PMIC has a built-in 32KHz oscillator which is used by PMC */
|
2021-12-12 00:14:03 +03:00
|
|
|
clk32k_in: clock-32k {
|
2020-06-29 05:54:52 +03:00
|
|
|
compatible = "fixed-clock";
|
|
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-frequency = <32768>;
|
|
|
|
|
clock-output-names = "pmic-oscillator";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cpus {
|
|
|
|
|
cpu0: cpu@0 {
|
|
|
|
|
cpu-supply = <&vdd_cpu>;
|
|
|
|
|
operating-points-v2 = <&cpu0_opp_table>;
|
|
|
|
|
#cooling-cells = <2>;
|
|
|
|
|
};
|
|
|
|
|
|
2021-03-02 15:09:59 +03:00
|
|
|
cpu1: cpu@1 {
|
2020-06-29 05:54:52 +03:00
|
|
|
cpu-supply = <&vdd_cpu>;
|
|
|
|
|
operating-points-v2 = <&cpu0_opp_table>;
|
2021-03-02 15:09:59 +03:00
|
|
|
#cooling-cells = <2>;
|
2020-06-29 05:54:52 +03:00
|
|
|
};
|
|
|
|
|
|
2021-03-02 15:09:59 +03:00
|
|
|
cpu2: cpu@2 {
|
2020-06-29 05:54:52 +03:00
|
|
|
cpu-supply = <&vdd_cpu>;
|
|
|
|
|
operating-points-v2 = <&cpu0_opp_table>;
|
2021-03-02 15:09:59 +03:00
|
|
|
#cooling-cells = <2>;
|
2020-06-29 05:54:52 +03:00
|
|
|
};
|
|
|
|
|
|
2021-03-02 15:09:59 +03:00
|
|
|
cpu3: cpu@3 {
|
2020-06-29 05:54:52 +03:00
|
|
|
cpu-supply = <&vdd_cpu>;
|
|
|
|
|
operating-points-v2 = <&cpu0_opp_table>;
|
2021-03-02 15:09:59 +03:00
|
|
|
#cooling-cells = <2>;
|
2020-06-29 05:54:52 +03:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
display-panel {
|
2020-11-04 17:12:51 +03:00
|
|
|
/*
|
2023-07-26 20:50:10 +02:00
|
|
|
* Some device variants come with a Hydis HV070WX2-1E0, but
|
|
|
|
|
* since they are all largely compatible, we'll go with the
|
|
|
|
|
* Chunghwa one here.
|
2020-11-04 17:12:51 +03:00
|
|
|
*/
|
2023-07-26 20:50:10 +02:00
|
|
|
compatible = "chunghwa,claa070wp03xg", "panel-lvds";
|
2020-06-29 05:54:52 +03:00
|
|
|
|
|
|
|
|
width-mm = <94>;
|
|
|
|
|
height-mm = <150>;
|
|
|
|
|
rotation = <180>;
|
|
|
|
|
|
|
|
|
|
data-mapping = "jeida-24";
|
|
|
|
|
|
2021-12-12 00:14:06 +03:00
|
|
|
/* DDC unconnected on Nexus 7 */
|
|
|
|
|
/delete-property/ ddc-i2c-bus;
|
2020-06-29 05:54:52 +03:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio-keys {
|
|
|
|
|
compatible = "gpio-keys";
|
|
|
|
|
|
2022-06-15 17:53:13 -07:00
|
|
|
key-power {
|
2020-06-29 05:54:52 +03:00
|
|
|
label = "Power";
|
|
|
|
|
gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
|
|
|
|
|
linux,code = <KEY_POWER>;
|
|
|
|
|
debounce-interval = <10>;
|
|
|
|
|
wakeup-event-action = <EV_ACT_ASSERTED>;
|
|
|
|
|
wakeup-source;
|
|
|
|
|
};
|
|
|
|
|
|
ARM: tegra: Sort nodes by unit-address, then alphabetically
Nodes in device tree should be sorted by unit-address, followed by nodes
without a unit-address, sorted alphabetically. Some exceptions are the
top-level aliases, chosen, firmware, memory and reserved-memory nodes,
which are expected to come first.
These rules apply recursively with some exceptions, such as pinmux nodes
or regulator nodes, which often follow more complicated ordering (often
by "importance").
While at it, change the name of some of the nodes to follow standard
naming conventions, which helps with the sorting order and reduces the
amount of warnings from the DT validation tools.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-22 11:21:18 +01:00
|
|
|
key-volume-down {
|
|
|
|
|
label = "Volume Down";
|
|
|
|
|
gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>;
|
|
|
|
|
linux,code = <KEY_VOLUMEDOWN>;
|
|
|
|
|
debounce-interval = <10>;
|
|
|
|
|
wakeup-event-action = <EV_ACT_ASSERTED>;
|
|
|
|
|
wakeup-source;
|
|
|
|
|
};
|
|
|
|
|
|
2022-06-15 17:53:13 -07:00
|
|
|
key-volume-up {
|
2020-06-29 05:54:52 +03:00
|
|
|
label = "Volume Up";
|
|
|
|
|
gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>;
|
|
|
|
|
linux,code = <KEY_VOLUMEUP>;
|
|
|
|
|
debounce-interval = <10>;
|
|
|
|
|
wakeup-event-action = <EV_ACT_ASSERTED>;
|
|
|
|
|
wakeup-source;
|
|
|
|
|
};
|
|
|
|
|
|
ARM: tegra: Sort nodes by unit-address, then alphabetically
Nodes in device tree should be sorted by unit-address, followed by nodes
without a unit-address, sorted alphabetically. Some exceptions are the
top-level aliases, chosen, firmware, memory and reserved-memory nodes,
which are expected to come first.
These rules apply recursively with some exceptions, such as pinmux nodes
or regulator nodes, which often follow more complicated ordering (often
by "importance").
While at it, change the name of some of the nodes to follow standard
naming conventions, which helps with the sorting order and reduces the
amount of warnings from the DT validation tools.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-22 11:21:18 +01:00
|
|
|
switch-hall-sensor {
|
|
|
|
|
label = "Lid";
|
|
|
|
|
gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>;
|
|
|
|
|
linux,input-type = <EV_SW>;
|
|
|
|
|
linux,code = <SW_LID>;
|
|
|
|
|
debounce-interval = <500>;
|
|
|
|
|
wakeup-event-action = <EV_ACT_DEASSERTED>;
|
2020-06-29 05:54:52 +03:00
|
|
|
wakeup-source;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
ARM: tegra: Sort nodes by unit-address, then alphabetically
Nodes in device tree should be sorted by unit-address, followed by nodes
without a unit-address, sorted alphabetically. Some exceptions are the
top-level aliases, chosen, firmware, memory and reserved-memory nodes,
which are expected to come first.
These rules apply recursively with some exceptions, such as pinmux nodes
or regulator nodes, which often follow more complicated ordering (often
by "importance").
While at it, change the name of some of the nodes to follow standard
naming conventions, which helps with the sorting order and reduces the
amount of warnings from the DT validation tools.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-22 11:21:18 +01:00
|
|
|
brcm_wifi_pwrseq: pwrseq-wifi {
|
|
|
|
|
compatible = "mmc-pwrseq-simple";
|
|
|
|
|
|
|
|
|
|
clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
|
|
|
|
|
clock-names = "ext_clock";
|
|
|
|
|
|
|
|
|
|
reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>;
|
|
|
|
|
post-power-on-delay-ms = <300>;
|
|
|
|
|
power-off-delay-us = <300>;
|
|
|
|
|
};
|
|
|
|
|
|
2021-12-12 00:14:04 +03:00
|
|
|
vdd_5v0_sys: regulator-5v0 {
|
2020-06-29 05:54:52 +03:00
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
regulator-name = "vdd_5v0";
|
|
|
|
|
regulator-min-microvolt = <5000000>;
|
|
|
|
|
regulator-max-microvolt = <5000000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
};
|
|
|
|
|
|
2021-12-12 00:14:04 +03:00
|
|
|
vdd_3v3_sys: regulator-3v3 {
|
2020-06-29 05:54:52 +03:00
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
regulator-name = "vdd_3v3";
|
|
|
|
|
regulator-min-microvolt = <3300000>;
|
|
|
|
|
regulator-max-microvolt = <3300000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
vin-supply = <&vdd_5v0_sys>;
|
|
|
|
|
};
|
|
|
|
|
|
2021-12-12 00:14:04 +03:00
|
|
|
vdd_pnl: regulator-panel {
|
2020-06-29 05:54:52 +03:00
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
regulator-name = "vdd_panel";
|
|
|
|
|
regulator-min-microvolt = <3300000>;
|
|
|
|
|
regulator-max-microvolt = <3300000>;
|
|
|
|
|
regulator-enable-ramp-delay = <300000>;
|
|
|
|
|
gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>;
|
|
|
|
|
enable-active-high;
|
|
|
|
|
vin-supply = <&vdd_3v3_sys>;
|
|
|
|
|
};
|
|
|
|
|
|
2021-12-12 00:14:04 +03:00
|
|
|
vcc_3v3_ts: regulator-ts {
|
2020-06-29 05:54:52 +03:00
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
regulator-name = "ldo_s-1167_3v3";
|
|
|
|
|
regulator-min-microvolt = <3300000>;
|
|
|
|
|
regulator-max-microvolt = <3300000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
vin-supply = <&vdd_5v0_sys>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sound {
|
|
|
|
|
compatible = "nvidia,tegra-audio-rt5640-grouper",
|
|
|
|
|
"nvidia,tegra-audio-rt5640";
|
|
|
|
|
nvidia,model = "ASUS Google Nexus 7 ALC5642";
|
|
|
|
|
|
|
|
|
|
nvidia,audio-routing =
|
|
|
|
|
"Headphones", "HPOR",
|
|
|
|
|
"Headphones", "HPOL",
|
|
|
|
|
"Speakers", "SPORP",
|
|
|
|
|
"Speakers", "SPORN",
|
|
|
|
|
"Speakers", "SPOLP",
|
|
|
|
|
"Speakers", "SPOLN",
|
|
|
|
|
"DMIC1", "Mic Jack";
|
|
|
|
|
|
|
|
|
|
nvidia,i2s-controller = <&tegra_i2s1>;
|
|
|
|
|
nvidia,audio-codec = <&rt5640>;
|
|
|
|
|
|
|
|
|
|
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
|
|
|
|
|
|
|
|
|
|
clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
|
|
|
|
|
<&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
|
|
|
|
|
<&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
|
|
|
|
|
clock-names = "pll_a", "pll_a_out0", "mclk";
|
|
|
|
|
|
|
|
|
|
assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
|
|
|
|
|
<&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
|
|
|
|
|
|
|
|
|
|
assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
|
|
|
|
|
<&tegra_car TEGRA30_CLK_EXTERN1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
thermal-zones {
|
2021-08-03 00:19:47 +03:00
|
|
|
/*
|
|
|
|
|
* NCT72 has two sensors:
|
|
|
|
|
*
|
|
|
|
|
* 0: internal that monitors ambient/skin temperature
|
|
|
|
|
* 1: external that is connected to the CPU's diode
|
|
|
|
|
*
|
|
|
|
|
* Ideally we should use userspace thermal governor,
|
|
|
|
|
* but it's a much more complex solution. The "skin"
|
|
|
|
|
* zone is a simpler solution which prevents Nexus 7
|
|
|
|
|
* from getting too hot from a user's tactile perspective.
|
|
|
|
|
* The CPU zone is intended to protect silicon from damage.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
skin-thermal {
|
2020-06-29 05:54:52 +03:00
|
|
|
polling-delay-passive = <1000>; /* milliseconds */
|
|
|
|
|
polling-delay = <5000>; /* milliseconds */
|
|
|
|
|
|
2021-08-03 00:19:47 +03:00
|
|
|
thermal-sensors = <&nct72 0>;
|
2020-06-29 05:54:52 +03:00
|
|
|
|
|
|
|
|
trips {
|
2021-08-03 00:19:47 +03:00
|
|
|
trip0: skin-alert {
|
2020-11-04 17:12:47 +03:00
|
|
|
/* throttle at 57C until temperature drops to 56.8C */
|
|
|
|
|
temperature = <57000>;
|
|
|
|
|
hysteresis = <200>;
|
2020-06-29 05:54:52 +03:00
|
|
|
type = "passive";
|
|
|
|
|
};
|
|
|
|
|
|
2021-08-03 00:19:47 +03:00
|
|
|
trip1: skin-crit {
|
2021-05-10 23:25:58 +03:00
|
|
|
/* shut down at 65C */
|
|
|
|
|
temperature = <65000>;
|
2020-06-29 05:54:52 +03:00
|
|
|
hysteresis = <2000>;
|
|
|
|
|
type = "critical";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cooling-maps {
|
|
|
|
|
map0 {
|
|
|
|
|
trip = <&trip0>;
|
2021-03-02 15:09:59 +03:00
|
|
|
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
|
|
|
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
|
|
|
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
2021-05-11 00:10:07 +03:00
|
|
|
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
|
|
|
<&actmon THERMAL_NO_LIMIT
|
|
|
|
|
THERMAL_NO_LIMIT>;
|
2020-06-29 05:54:52 +03:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
2021-08-03 00:19:47 +03:00
|
|
|
|
|
|
|
|
cpu-thermal {
|
|
|
|
|
polling-delay-passive = <1000>; /* milliseconds */
|
|
|
|
|
polling-delay = <5000>; /* milliseconds */
|
|
|
|
|
|
|
|
|
|
thermal-sensors = <&nct72 1>;
|
|
|
|
|
|
|
|
|
|
trips {
|
|
|
|
|
trip2: cpu-alert {
|
|
|
|
|
/* throttle at 85C until temperature drops to 84.8C */
|
|
|
|
|
temperature = <85000>;
|
|
|
|
|
hysteresis = <200>;
|
|
|
|
|
type = "passive";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
trip3: cpu-crit {
|
|
|
|
|
/* shut down at 90C */
|
|
|
|
|
temperature = <90000>;
|
|
|
|
|
hysteresis = <2000>;
|
|
|
|
|
type = "critical";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cooling-maps {
|
|
|
|
|
map1 {
|
|
|
|
|
trip = <&trip2>;
|
|
|
|
|
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
|
|
|
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
|
|
|
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
|
|
|
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
|
|
|
<&actmon THERMAL_NO_LIMIT
|
|
|
|
|
THERMAL_NO_LIMIT>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
2020-06-29 05:54:52 +03:00
|
|
|
};
|
|
|
|
|
};
|
