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63 lines
2.2 KiB
ReStructuredText
63 lines
2.2 KiB
ReStructuredText
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.. SPDX-License-Identifier: GPL-2.0
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================================
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CEDT - CXL Early Discovery Table
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================================
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The CXL Early Discovery Table is generated by BIOS to describe the CXL memory
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regions configured at boot by the BIOS.
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CHBS
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====
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The CXL Host Bridge Structure describes CXL host bridges. Other than describing
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device register information, it reports the specific host bridge UID for this
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host bridge. These host bridge ID's will be referenced in other tables.
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Example ::
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Subtable Type : 00 [CXL Host Bridge Structure]
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Reserved : 00
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Length : 0020
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Associated host bridge : 00000007 <- Host bridge _UID
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Specification version : 00000001
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Reserved : 00000000
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Register base : 0000010370400000
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Register length : 0000000000010000
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CFMWS
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=====
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The CXL Fixed Memory Window structure describes a memory region associated
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with one or more CXL host bridges (as described by the CHBS). It additionally
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describes any inter-host-bridge interleave configuration that may have been
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programmed by BIOS.
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Example ::
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Subtable Type : 01 [CXL Fixed Memory Window Structure]
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Reserved : 00
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Length : 002C
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Reserved : 00000000
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Window base address : 000000C050000000 <- Memory Region
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Window size : 0000003CA0000000
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Interleave Members (2^n) : 01 <- Interleave configuration
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Interleave Arithmetic : 00
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Reserved : 0000
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Granularity : 00000000
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Restrictions : 0006
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QtgId : 0001
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First Target : 00000007 <- Host Bridge _UID
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Next Target : 00000006 <- Host Bridge _UID
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The restriction field dictates what this SPA range may be used for (memory type,
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voltile vs persistent, etc). One or more bits may be set. ::
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Bit[0]: CXL Type 2 Memory
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Bit[1]: CXL Type 3 Memory
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Bit[2]: Volatile Memory
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Bit[3]: Persistent Memory
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Bit[4]: Fixed Config (HPA cannot be re-used)
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INTRA-host-bridge interleave (multiple devices on one host bridge) is NOT
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reported in this structure, and is solely defined via CXL device decoder
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programming (host bridge and endpoint decoders).
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