mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-08-20 06:20:41 +00:00
53 lines
1.1 KiB
YAML
53 lines
1.1 KiB
YAML
![]() |
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||
|
%YAML 1.2
|
||
|
---
|
||
|
$id: http://devicetree.org/schemas/interrupt-controller/qca,ar7100-misc-intc.yaml#
|
||
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||
|
|
||
|
title: Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller
|
||
|
|
||
|
maintainers:
|
||
|
- Alban Bedel <albeu@free.fr>
|
||
|
- Alexander Couzens <lynxis@fe80.eu>
|
||
|
|
||
|
description:
|
||
|
The Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller is a secondary
|
||
|
controller for lower priority interrupts.
|
||
|
|
||
|
properties:
|
||
|
compatible:
|
||
|
oneOf:
|
||
|
- items:
|
||
|
- const: qca,ar9132-misc-intc
|
||
|
- const: qca,ar7100-misc-intc
|
||
|
- const: qca,ar7240-misc-intc
|
||
|
reg:
|
||
|
maxItems: 1
|
||
|
|
||
|
interrupts:
|
||
|
maxItems: 1
|
||
|
|
||
|
interrupt-controller: true
|
||
|
|
||
|
'#interrupt-cells':
|
||
|
const: 1
|
||
|
|
||
|
additionalProperties: false
|
||
|
|
||
|
required:
|
||
|
- compatible
|
||
|
- reg
|
||
|
- interrupts
|
||
|
- interrupt-controller
|
||
|
- "#interrupt-cells"
|
||
|
|
||
|
examples:
|
||
|
- |
|
||
|
interrupt-controller@18060010 {
|
||
|
compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc";
|
||
|
reg = <0x18060010 0x4>;
|
||
|
interrupts = <6>;
|
||
|
interrupt-controller;
|
||
|
#interrupt-cells = <1>;
|
||
|
};
|