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75 lines
1.6 KiB
YAML
75 lines
1.6 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/fpga/altr,fpga-passive-serial.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Altera Passive Serial SPI FPGA Manager
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maintainers:
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- Fabio Estevam <festevam@denx.de>
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description: |
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Altera FPGAs support a method of loading the bitstream over what is
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referred to as "passive serial".
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The passive serial link is not technically SPI, and might require extra
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circuits in order to play nicely with other SPI slaves on the same bus.
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See https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf
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allOf:
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- $ref: /schemas/spi/spi-peripheral-props.yaml#
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properties:
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compatible:
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enum:
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- altr,fpga-passive-serial
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- altr,fpga-arria10-passive-serial
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spi-max-frequency:
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maximum: 20000000
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reg:
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maxItems: 1
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nconfig-gpios:
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description:
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Config pin (referred to as nCONFIG in the manual).
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maxItems: 1
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nstat-gpios:
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description:
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Status pin (referred to as nSTATUS in the manual).
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maxItems: 1
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confd-gpios:
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description:
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confd pin (referred to as CONF_DONE in the manual)
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maxItems: 1
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required:
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- compatible
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- reg
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- nconfig-gpios
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- nstat-gpios
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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fpga@0 {
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compatible = "altr,fpga-passive-serial";
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reg = <0>;
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nconfig-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
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nstat-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
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confd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
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};
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};
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...
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