linux/arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi

// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
 * Device Tree Source for the RZ/V2L R9A07G054L2 SoC specific parts
 *
 * Copyright (C) 2021 Renesas Electronics Corp.
 */

/dts-v1/;
#include "r9a07g054.dtsi"

/ {
	compatible = "renesas,r9a07g054l2", "renesas,r9a07g054";
};
arm64: dts: renesas: Add initial DTSI for RZ/V2L SoC The RZ/V2L SoC is package- and pin-compatible with RZ/G2L, the only difference being that the RZ/V2L SoC has additional DRP-AI IP (AI accelerator). Add initial DTSI for the RZ/V2L SoC with below SoC specific dtsi files for supporting single core and dual core devices: r9a07g054l1.dtsi => RZ/V2L R9A07G054L1 SoC specific parts r9a07g054l2.dtsi => RZ/V2L R9A07G054L2 SoC specific parts Both the RZ/G2L and RZ/V2L SMARC EVK SoMs are identical apart from the SoCs used, hence the common dtsi files (rzg2l-smarc*.dtsi) are shared between the RZ/G2L and RZ/V2L SMARC EVKs. Place holders are added in device nodes to avoid compilation errors for devices which have not been enabled yet on the RZ/V2L SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220110134659.30424-11-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> 2022-01-10 13:46:57 +00:00			`// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)`
			`/*`
			`* Device Tree Source for the RZ/V2L R9A07G054L2 SoC specific parts`
			`*`
			`* Copyright (C) 2021 Renesas Electronics Corp.`
			`*/`

			`/dts-v1/;`
			`#include "r9a07g054.dtsi"`

			`/ {`
			`compatible = "renesas,r9a07g054l2", "renesas,r9a07g054";`
			`};`