2019-06-04 10:11:33 +02:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2015-04-04 16:58:38 +01:00
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/*
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* Copyright (C) 2015 Russell King
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*
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* This assembly is required to safely remap the physical address space
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* for Keystone 2
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*/
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#include <linux/linkage.h>
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2020-06-08 21:32:42 -07:00
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#include <linux/pgtable.h>
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2015-04-04 16:58:38 +01:00
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#include <asm/asm-offsets.h>
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#include <asm/cp15.h>
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ARM: mm: Make virt_to_pfn() a static inline
Making virt_to_pfn() a static inline taking a strongly typed
(const void *) makes the contract of a passing a pointer of that
type to the function explicit and exposes any misuse of the
macro virt_to_pfn() acting polymorphic and accepting many types
such as (void *), (unitptr_t) or (unsigned long) as arguments
without warnings.
Doing this is a bit intrusive: virt_to_pfn() requires
PHYS_PFN_OFFSET and PAGE_SHIFT to be defined, and this is defined in
<asm/page.h>, so this must be included *before* <asm/memory.h>.
The use of macros were obscuring the unclear inclusion order here,
as the macros would eventually be resolved, but a static inline
like this cannot be compiled with unresolved macros.
The naive solution to include <asm/page.h> at the top of
<asm/memory.h> does not work, because <asm/memory.h> sometimes
includes <asm/page.h> at the end of itself, which would create a
confusing inclusion loop. So instead, take the approach to always
unconditionally include <asm/page.h> at the end of <asm/memory.h>
arch/arm uses <asm/memory.h> explicitly in a lot of places,
however it turns out that if we just unconditionally include
<asm/memory.h> into <asm/page.h> and switch all inclusions of
<asm/memory.h> to <asm/page.h> instead, we enforce the right
order and <asm/memory.h> will always have access to the
definitions.
Put an inclusion guard in place making it impossible to include
<asm/memory.h> explicitly.
Link: https://lore.kernel.org/linux-mm/20220701160004.2ffff4e5ab59a55499f4c736@linux-foundation.org/
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-06-02 10:18:32 +02:00
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#include <asm/page.h>
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2015-04-04 16:58:38 +01:00
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.section ".idmap.text", "ax"
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#define L1_ORDER 3
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#define L2_ORDER 3
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ENTRY(lpae_pgtables_remap_asm)
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stmfd sp!, {r4-r8, lr}
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mrc p15, 0, r8, c1, c0, 0 @ read control reg
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bic ip, r8, #CR_M @ disable caches and MMU
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mcr p15, 0, ip, c1, c0, 0
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dsb
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isb
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/* Update level 2 entries covering the kernel */
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ldr r6, =(_end - 1)
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add r7, r2, #0x1000
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add r6, r7, r6, lsr #SECTION_SHIFT - L2_ORDER
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2021-08-09 12:57:19 +01:00
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add r7, r7, #KERNEL_OFFSET >> (SECTION_SHIFT - L2_ORDER)
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2018-11-09 04:26:39 +01:00
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1: ldrd r4, r5, [r7]
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2015-04-04 16:58:38 +01:00
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adds r4, r4, r0
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adc r5, r5, r1
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2018-11-09 04:26:39 +01:00
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strd r4, r5, [r7], #1 << L2_ORDER
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2015-04-04 16:58:38 +01:00
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cmp r7, r6
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bls 1b
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/* Update level 2 entries for the boot data */
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add r7, r2, #0x1000
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ARM: 9012/1: move device tree mapping out of linear region
On ARM, setting up the linear region is tricky, given the constraints
around placement and alignment of the memblocks, and how the kernel
itself as well as the DT are placed in physical memory.
Let's simplify matters a bit, by moving the device tree mapping to the
top of the address space, right between the end of the vmalloc region
and the start of the the fixmap region, and create a read-only mapping
for it that is independent of the size of the linear region, and how it
is organized.
Since this region was formerly used as a guard region, which will now be
populated fully on LPAE builds by this read-only mapping (which will
still be able to function as a guard region for stray writes), bump the
start of the [underutilized] fixmap region by 512 KB as well, to ensure
that there is always a proper guard region here. Doing so still leaves
ample room for the fixmap space, even with NR_CPUS set to its maximum
value of 32.
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2020-10-11 10:21:37 +01:00
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movw r3, #FDT_FIXED_BASE >> (SECTION_SHIFT - L2_ORDER)
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add r7, r7, r3
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2018-11-09 04:26:39 +01:00
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ldrd r4, r5, [r7]
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2015-04-04 16:58:38 +01:00
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adds r4, r4, r0
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adc r5, r5, r1
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2018-11-09 04:26:39 +01:00
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strd r4, r5, [r7], #1 << L2_ORDER
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ldrd r4, r5, [r7]
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2015-04-04 16:58:38 +01:00
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adds r4, r4, r0
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adc r5, r5, r1
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2018-11-09 04:26:39 +01:00
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strd r4, r5, [r7]
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2015-04-04 16:58:38 +01:00
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/* Update level 1 entries */
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mov r6, #4
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mov r7, r2
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2018-11-09 04:26:39 +01:00
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2: ldrd r4, r5, [r7]
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2015-04-04 16:58:38 +01:00
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adds r4, r4, r0
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adc r5, r5, r1
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2018-11-09 04:26:39 +01:00
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strd r4, r5, [r7], #1 << L1_ORDER
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2015-04-04 16:58:38 +01:00
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subs r6, r6, #1
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bne 2b
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mrrc p15, 0, r4, r5, c2 @ read TTBR0
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adds r4, r4, r0 @ update physical address
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adc r5, r5, r1
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mcrr p15, 0, r4, r5, c2 @ write back TTBR0
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mrrc p15, 1, r4, r5, c2 @ read TTBR1
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adds r4, r4, r0 @ update physical address
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adc r5, r5, r1
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mcrr p15, 1, r4, r5, c2 @ write back TTBR1
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dsb
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mov ip, #0
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mcr p15, 0, ip, c7, c5, 0 @ I+BTB cache invalidate
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mcr p15, 0, ip, c8, c7, 0 @ local_flush_tlb_all()
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dsb
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isb
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mcr p15, 0, r8, c1, c0, 0 @ re-enable MMU
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dsb
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isb
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ldmfd sp!, {r4-r8, pc}
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ENDPROC(lpae_pgtables_remap_asm)
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