ARM: dts: qcom: Add SDX65 platform and MTP board support
Add basic devicetree support for SDX65 platform and MTP board from
Qualcomm. The SDX65 platform features an ARM Cortex A7 CPU which forms
the Application Processor Sub System (APSS) along with standard Qualcomm
peripherals like GCC, TLMM, BLSP, QPIC, and BAM etc... Also, there
exists the networking parts such as IPA, MHI, PCIE-EP, EMAC, and Modem
etc..
This commit adds basic devicetree support that includes GCC, RPMh clock, INTC
and Debug UART.
Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1635552125-16407-3-git-send-email-quic_vamslank@quicinc.com
2021-10-29 17:02:04 -07:00
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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/dts-v1/;
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2023-09-21 08:34:02 +02:00
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/* PM7250B is configured to use SID2/3 */
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#define PM7250B_SID 2
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#define PM7250B_SID1 3
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ARM: dts: qcom: Add SDX65 platform and MTP board support
Add basic devicetree support for SDX65 platform and MTP board from
Qualcomm. The SDX65 platform features an ARM Cortex A7 CPU which forms
the Application Processor Sub System (APSS) along with standard Qualcomm
peripherals like GCC, TLMM, BLSP, QPIC, and BAM etc... Also, there
exists the networking parts such as IPA, MHI, PCIE-EP, EMAC, and Modem
etc..
This commit adds basic devicetree support that includes GCC, RPMh clock, INTC
and Debug UART.
Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1635552125-16407-3-git-send-email-quic_vamslank@quicinc.com
2021-10-29 17:02:04 -07:00
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#include "qcom-sdx65.dtsi"
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2022-03-16 11:47:27 +05:30
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#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
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2022-03-16 11:47:23 +05:30
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#include <arm64/qcom/pmk8350.dtsi>
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2023-08-07 19:08:51 +05:30
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#include <arm64/qcom/pm7250b.dtsi>
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2023-09-28 14:02:40 +03:00
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#include "pmx65.dtsi"
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ARM: dts: qcom: Add SDX65 platform and MTP board support
Add basic devicetree support for SDX65 platform and MTP board from
Qualcomm. The SDX65 platform features an ARM Cortex A7 CPU which forms
the Application Processor Sub System (APSS) along with standard Qualcomm
peripherals like GCC, TLMM, BLSP, QPIC, and BAM etc... Also, there
exists the networking parts such as IPA, MHI, PCIE-EP, EMAC, and Modem
etc..
This commit adds basic devicetree support that includes GCC, RPMh clock, INTC
and Debug UART.
Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1635552125-16407-3-git-send-email-quic_vamslank@quicinc.com
2021-10-29 17:02:04 -07:00
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/ {
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model = "Qualcomm Technologies, Inc. SDX65 MTP";
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compatible = "qcom,sdx65-mtp", "qcom,sdx65";
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qcom,board-id = <0x2010008 0x302>;
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aliases {
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serial0 = &blsp1_uart3;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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2022-03-16 11:47:27 +05:30
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2022-04-11 15:20:09 +05:30
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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mpss_dsm: memory@8c400000 {
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no-map;
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reg = <0x8c400000 0x3200000>;
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};
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ipa_fw_mem: memory@8fced000 {
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no-map;
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reg = <0x8fced000 0x10000>;
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};
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mpss_adsp_mem: memory@90800000 {
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no-map;
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reg = <0x90800000 0x10000000>;
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};
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};
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2022-03-16 11:47:27 +05:30
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vph_pwr: vph-pwr-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vph_pwr";
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regulator-min-microvolt = <3700000>;
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regulator-max-microvolt = <3700000>;
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};
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vreg_bob_3p3: pmx65_bob {
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compatible = "regulator-fixed";
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regulator-name = "vreg_bob_3p3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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regulator-boot-on;
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vin-supply = <&vph_pwr>;
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};
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ARM: dts: qcom: Add SDX65 platform and MTP board support
Add basic devicetree support for SDX65 platform and MTP board from
Qualcomm. The SDX65 platform features an ARM Cortex A7 CPU which forms
the Application Processor Sub System (APSS) along with standard Qualcomm
peripherals like GCC, TLMM, BLSP, QPIC, and BAM etc... Also, there
exists the networking parts such as IPA, MHI, PCIE-EP, EMAC, and Modem
etc..
This commit adds basic devicetree support that includes GCC, RPMh clock, INTC
and Debug UART.
Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1635552125-16407-3-git-send-email-quic_vamslank@quicinc.com
2021-10-29 17:02:04 -07:00
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};
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2022-03-16 11:47:27 +05:30
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&apps_rsc {
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2023-01-27 12:43:38 +01:00
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regulators-0 {
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2022-03-16 11:47:27 +05:30
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compatible = "qcom,pmx65-rpmh-regulators";
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qcom,pmic-id = "b";
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vdd-s1-supply = <&vph_pwr>;
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vdd-s2-supply = <&vph_pwr>;
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vdd-s3-supply = <&vph_pwr>;
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vdd-s4-supply = <&vph_pwr>;
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vdd-s5-supply = <&vph_pwr>;
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vdd-s6-supply = <&vph_pwr>;
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vdd-s7-supply = <&vph_pwr>;
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vdd-s8-supply = <&vph_pwr>;
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vdd-l1-supply = <&vreg_s2b_1p224>;
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vdd-l2-l18-supply = <&vreg_s2b_1p224>;
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vdd-l3-supply = <&vreg_s8b_0p824>;
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vdd-l4-supply = <&vreg_s7b_0p936>;
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vdd-l5-l6-l16-supply = <&vreg_s4b_1p824>;
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vdd-l7-supply = <&vreg_s3b_0p776>;
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vdd-l8-l9-supply = <&vreg_s8b_0p824>;
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vdd-l10-supply = <&vreg_bob_3p3>;
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vdd-l11-l13-supply = <&vreg_bob_3p3>;
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vdd-l12-supply = <&vreg_s2b_1p224>;
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vdd-l14-supply = <&vreg_s3b_0p776>;
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vdd-l15-supply = <&vreg_s2b_1p224>;
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vdd-l17-supply = <&vreg_s8b_0p824>;
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vdd-l19-supply = <&vreg_s3b_0p776>;
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vdd-l20-supply = <&vreg_s7b_0p936>;
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vdd-l21-supply = <&vreg_s7b_0p936>;
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vreg_s2b_1p224: smps2 {
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1400000>;
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};
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vreg_s3b_0p776: smps3 {
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <1040000>;
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};
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vreg_s4b_1p824: smps4 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <2024000>;
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};
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vreg_s7b_0p936: smps7 {
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <1040000>;
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};
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vreg_s8b_0p824: smps8 {
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regulator-min-microvolt = <304000>;
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regulator-max-microvolt = <1300000>;
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};
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2022-05-02 14:36:35 +05:30
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vreg_l1b_1p2: ldo1 {
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2022-03-16 11:47:27 +05:30
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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};
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ldo2 {
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regulator-min-microvolt = <1128000>;
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regulator-max-microvolt = <1128000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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};
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ldo3 {
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regulator-min-microvolt = <300000>;
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regulator-max-microvolt = <960000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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};
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2022-05-02 14:36:35 +05:30
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vreg_l4b_0p88: ldo4 {
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2022-03-16 11:47:27 +05:30
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regulator-min-microvolt = <880000>;
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regulator-max-microvolt = <912000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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};
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2022-05-02 14:36:35 +05:30
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vreg_l5b_1p8: ldo5 {
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2022-03-16 11:47:27 +05:30
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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};
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ldo6 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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};
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ldo7 {
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regulator-min-microvolt = <752000>;
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regulator-max-microvolt = <752000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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};
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ldo8 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <800000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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};
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ldo9 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <800000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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};
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2022-05-02 14:36:35 +05:30
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vreg_l10b_3p08: ldo10 {
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2022-03-16 11:47:27 +05:30
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regulator-min-microvolt = <3088000>;
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regulator-max-microvolt = <3088000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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};
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ldo11 {
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regulator-min-microvolt = <1704000>;
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regulator-max-microvolt = <2928000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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};
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ldo12 {
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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};
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ldo13 {
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regulator-min-microvolt = <1704000>;
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regulator-max-microvolt = <2928000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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};
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ldo14 {
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <800000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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};
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ldo15 {
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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};
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ldo16 {
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regulator-min-microvolt = <1776000>;
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regulator-max-microvolt = <1776000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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};
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ldo17 {
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regulator-min-microvolt = <300000>;
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regulator-max-microvolt = <960000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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};
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ldo19 {
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regulator-min-microvolt = <752000>;
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regulator-max-microvolt = <752000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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};
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ldo20 {
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regulator-min-microvolt = <912000>;
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regulator-max-microvolt = <912000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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};
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ldo21 {
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regulator-min-microvolt = <912000>;
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regulator-max-microvolt = <912000>;
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regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
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};
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};
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};
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2022-05-02 14:36:35 +05:30
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2022-05-02 10:08:05 -07:00
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&blsp1_uart3 {
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status = "okay";
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};
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2023-03-27 14:56:04 -05:00
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&ipa {
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qcom,gsi-loader = "skip";
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status = "okay";
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};
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2023-05-18 23:17:53 +05:30
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&pcie_ep {
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pinctrl-0 = <&pcie_ep_clkreq_default
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&pcie_ep_perst_default
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&pcie_ep_wake_default>;
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pinctrl-names = "default";
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reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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2023-05-18 23:17:52 +05:30
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&pcie_phy {
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vdda-phy-supply = <&vreg_l1b_1p2>;
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vdda-pll-supply = <&vreg_l4b_0p88>;
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status = "okay";
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};
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2022-05-02 10:08:05 -07:00
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&qpic_bam {
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status = "okay";
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};
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2022-05-02 10:08:06 -07:00
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&qpic_nand {
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status = "okay";
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nand@0 {
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reg = <0>;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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nand-bus-width = <8>;
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/* ico and efs2 partitions are secured */
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secure-regions = /bits/ 64 <0x500000 0x500000
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0xa00000 0xb00000>;
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};
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};
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2022-06-01 16:15:08 +05:30
|
|
|
&remoteproc_mpss {
|
|
|
|
memory-region = <&mpss_adsp_mem>;
|
2023-03-27 14:56:05 -05:00
|
|
|
status = "okay";
|
2022-06-01 16:15:08 +05:30
|
|
|
};
|
|
|
|
|
2023-05-18 23:17:53 +05:30
|
|
|
&tlmm {
|
|
|
|
pcie_ep_clkreq_default: pcie-ep-clkreq-default-state {
|
|
|
|
pins = "gpio56";
|
|
|
|
function = "pcie_clkreq";
|
|
|
|
drive-strength = <2>;
|
|
|
|
bias-disable;
|
|
|
|
};
|
|
|
|
|
|
|
|
pcie_ep_perst_default: pcie-ep-perst-default-state {
|
|
|
|
pins = "gpio57";
|
|
|
|
function = "gpio";
|
|
|
|
drive-strength = <2>;
|
|
|
|
bias-pull-down;
|
|
|
|
};
|
|
|
|
|
|
|
|
pcie_ep_wake_default: pcie-ep-wake-default-state {
|
|
|
|
pins = "gpio53";
|
|
|
|
function = "gpio";
|
|
|
|
drive-strength = <2>;
|
|
|
|
bias-disable;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
2022-05-02 14:36:35 +05:30
|
|
|
&usb {
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|
|
|
|
&usb_dwc3 {
|
|
|
|
dr_mode = "peripheral";
|
|
|
|
};
|
|
|
|
|
|
|
|
&usb_hsphy {
|
|
|
|
vdda-pll-supply = <&vreg_l4b_0p88>;
|
|
|
|
vdda33-supply = <&vreg_l10b_3p08>;
|
|
|
|
vdda18-supply = <&vreg_l5b_1p8>;
|
2023-03-27 14:56:05 -05:00
|
|
|
status = "okay";
|
2022-05-02 14:36:35 +05:30
|
|
|
};
|
|
|
|
|
|
|
|
&usb_qmpphy {
|
|
|
|
vdda-phy-supply = <&vreg_l4b_0p88>;
|
|
|
|
vdda-pll-supply = <&vreg_l1b_1p2>;
|
2023-03-27 14:56:05 -05:00
|
|
|
status = "okay";
|
2022-05-02 14:36:35 +05:30
|
|
|
};
|